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8259A PIC
Able to handle a number of interrupts at a time. Takes care of a number of simultaneously appearing interrupt requests along with their types and priorities. Compatible with 8-bit as well as 16-bit processors.
IRR
8 interrupt inputs set corresponding bits of IRR Used to store the information about the interrupt inputs requesting service.
ISR
Used to store information about the interrupts currently being serviced. * OCWs Operation Control Word.
PRIORITY RESOLVER
Determines the priorities of interrupts requesting services (which set corresponding bits of IRR) It determines the priorities as dictated by priority mode set by OCWs. The bit corresponding to highest priority input is set in ISR during input. Examines three registers and determines whether INT should be sent to MPU.
IMR
This register can be programmed by an OCW to store the bits which mask specific interrupts. IMR operates on the IRR. An interrupt which is masked by software (By programming the IMR) will not be recognized and serviced even if it sets corresponding bits in the IRR.
For 8085 system they are filled by A15-A11 of the interrupt vector address and Least significant 3 bits are same as the respective bits of the vector address. For 8086 system they are filled by most significant 5 bits of interrupt type and the least significant 3 bits are 0, pointing to IR0.
If BUF=0,M/S is to be neglected.
AUTOMATIC ROTATION MODE: In this mode, a device after being serviced, receives the lowest priority. SPECIFIC ROTATION MODE: Similar to automatic rotation mode, except that the user can select any IR for the lowest priority, thus fixing all other priorities.
INTERRUPT STATUS: The status of the three interrupt registers (IRR, ISR and IMR) can be read, and this status information can be used to make the interrupt process versatile.
POLL METHOD: 8259A can be set up to function in polled environment. MPU polls the 8259A rather than each peripheral.