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DESIGN OF THE BASIC PROCESSING UNIT

BOOK : COMPUTER ORGANISATION Carl Hamacher Zvonko Vrane !c Sa"#a$ Zak%

Topics Under Review How a processor executes instructions The interna !unctiona units o! a processor an" how the# are interconnecte"$ Har"ware !or %eneratin% interna contro si%na s The &icropro%ra&&in% approach 'icropro%ra& or%ani(ation

Processing Unit The CPU executes a sequence of instructions. The execution of an instruction is organized as an instruction cycle: it is performed as a succession of several steps; Each step is executed as a set of several microoperations.

Instruction Execution
The processor !etches one instruction at a ti&e an" per!or&s the operations speci!ie"$ Instructions are !etche" !ro& successi)e &e&or# ocations unti a *ranch or a +u&p instruction is encountere"$ The Pro%ra& Counter ,PC- re%ister .eeps trac. o! the a""ress o! the &e&or# ocation !ro& where the next instruction is to *e !etche"$ PC is up"ate" a!ter each instruction is !etche"$ One instruct &a# occup# &ore than one wor" / re0uirin% &ore than one !etch operation$

Basic Instruction Cycle


&tart etch the next !nstruction "ecode !nstruction #pcode etch Cycle

"ecode Cycle

No

!f #perand$s% required

Yes
etch #perand$s% Execute !nstruction &top #perand etch Cycle

Execute Cycle

Sin% e Bus Or%anisation o! a Processor


Control signals .... !nstruction "ecoder and Control logic !nternal Processor 0us

PC (ddress 1ines 'emory 0us "ata 1ines Constant 2alue &elect 'U/ '() '") *

!) ), . . . )$n-.% TE'P

(1U Control 1ines

(dd &u3 . /#)


. .

( (1U

Carry !n +

Instruction Execution
The tas4 performed 3y any microoperation falls in one of the follo5ing categories:
Transfer data from one register to another; Transfer data from a register to an external interface $system 3us%; Transfer data from an external interface to a register; Perform an arithmetic or logic operation6 using registers for input and output.

Control Signals
The CPU executes an instruction as a se uence o! control steps" In each control step one or several #icrooperations are executed" $ne cloc% pulse triggers the activities corresponding to one control step & !or each cloc% pulse the control unit generates the control signals corresponding to the #icrooperations to 'e executed in the respective control step

Input an" Output Gatin% !or the Re%isters


Riin
/ Ri /

Riout Yin
/ !nternal Processor 0us

7 7 7 7

Constant Select
'U/ (

R( R) R)$UT * ) P+,CE o-p o! R) T$ BU. R(I/ * ) +$,0. 0,T, 1R$M BU. T$ R(

0 (1U

Zin

/ Z /

Zout

I/p and O/p Gating for One Register Bit

Control Signals
In or"er to a ow the execution o! a microoperation1 one or se)era control signals ha)e to *e issue"2 the# a ow the correspon"in% "ata trans!er an"3or co&putation to *e per!or&e"$ Exa&p es4 a- si%na s !or trans!errin% content o! re%ister R5 to R64 R5out1 R6in *- si%na s !or a""in% content o! 7 to that o! R5 ,resu t in 8-4 R5out1 A""1 8in c- si%na s !or rea"in% a &e&or# ocation2 a""ress in R94 R9out1 'ARin1 Rea"

Register Trans!ers Instruction execution in)o )es a series o! steps in which "ata are trans!erre" !ro& one re%ister to another$ For each re%ister1 two contro si%na s are use" to p ace the contents o! the re%ister on to the *us or or to oa" the "ata on the *us into the re%isters$

Re%ister Trans!er
Ti&in% o! a processor operations an" "ata trans!ers within the processor "e!ine" *# the processor c oc.$ Contro si%na s are asserte" at the *e%innin% o! the c oc. c#c e$ The re%isters are &a"e o! e"%e tri%%ere" ! ip ! ops$ Exa&p e R: R6

Per!or#ing an , or + operation
A;U has no interna stora%e$ One I3p co&es !ro& the O3p o! 'ux an" the other co&es "irect # !ro& the *us$ The resu ts are te&porari # store" in 8$ The contro si%na s are acti)ate" !or the "uration o! the c oc. c#c e correspon"in% to the step1 a other si%na s are inacti)e$ R9 R6 < R=
R6OUT 1 7IN R=OUT 1 SE;ECT 7 1 ADD 1 8IN 8OUT 1 R9IN

1etching a 2ord !ro# Me#ory


The processor has to speci!# the re0uire" &e&or# a""ress an" re0uest a READ operation$ The re0uire" a""ress is trans!erre" to 'AR whose o3p is connecte" to the a""ress ines o! the &e&or# *us$ Processor uses the contro ines o! the &e&or# *us to in"icate that a READ operation is re0uire"$ The "ata rea" !ro& the &e&or# are store" in 'DR !ro& where the# can *e trans!erre" to where the# are nee"e"$

'emory 0us "ata 1ines '")outE /

!nternal Processor 0us '")out /

MDR

/ '")inE

/ '")in

Connection and control signals !or the register M0R

Exa#ple For R= '>R6?


6$ =$ 9$ :$ A$
6$ =$ 9$

'AR>R6? Start rea" on &e&or# *us @ait !or 'e&or# Function Co&p ete" ,'FC- !ro& &e&or# ;oa" 'DR !ro& *us R=>'DR?
R6out1 'ARin1 Rea" 'DRinE1 @'FC ,wait !or 'FC'DRout1R=in

Si%na s *ein% Acti)ate"

Co&p ete Instruction Execution Exa&p e ADD R61 '>R9? A""s the contents o! the &e&or# ocation pointe" to *# R9 to re%ister R6$
Fetch the instruction Fetch the !irst operan" ,the contents o! the &e&or# ocation pointe" to *# R9 Per!or& the a""ition$ ;oa" the resu t into R6

Sin% e Bus Or%anisation o! a Processor


Control signals .... !nstruction "ecoder and Control logic !nternal Processor 0us

PC (ddress 1ines 'emory 0us "ata 1ines Constant 2alue &elect 'U/ '() '") *

!) ), . . . )$n-.% TE'P

(1U Control 1ines

(dd &u3 . /#)


. .

( (1U

Carry !n +

Control .e uence !or ,00 R)3 M@R;A


Instruction 1etch Phase )" PC loaded into M,R3 read re uest to #e#ory3 MU4 gives (3added to B 5PC6 and stored in 7 PC$UT3 M,RI/3 RE,03 .E+ECT8(3 ,003 7I/ 7 #oved to PC while waiting !or #e#ory 7$UT3 PCI/3 :I/3 2M1C 2ord !etched !ro# #e#ory and loaded into IR M0R$UT3 IRI/ R; trans!erred to M,R and #e#ory read operation initiated R;$UT3 M,RI/3 RE,0 contents o! R) #oved to : R)$UT3 :I/3 2M1C read operation co#pleted and is in M0R as well as B input o! ,+U" .elect: as second input o! ,+U and add per!or#ed M0R$UT3 .E+ECT8:3 ,003 7I/

9" ;"

1igure out what the instruction should do and set control circuitry !or steps (8<" <" =" >"

)?" result is trans!erred to R)3 End causes a goto step ) 7$UT3 R)I/3 E/0

Pro'le#
Assu&in% a &e&or# rea" or write operation ta.es the sa&e ti&e as one interna processor step an" that *oth the processor an" the &e&or# are contro e" *# the sa&e c oc.$ Esti&ate execution ti&eB @hat wi *e the execution ti&e i! the &e&or# access ti&e is e0ua to twice the processor c oc. perio"$

< cloc%s

> cloc%s

Pro'le#s 'ased on .ingle Bus structure

Assu&in% that each instruction consists o! two wor"s$ The !irst wor" speci!ies the operation an" the secon" wor" contains the nu&*er NU'$ A so assu&e a sin% e *us structure as "iscusse"$ @rite the se0uence o! contro steps re0uire" !or4 a- A"" the nu&*er NU' to re%ister R6 *- A"" the contents o! &e&or# ocation NU' to re%ister R6 c- A"" the contents o! the &e&or# ocation whose a""ress is at the &e&or# ocation NU' to re%ister R6

,dd the nu#'er /UM to register R)

6$ =$ 9$ :$ A$ C$ D$ E$

PCout1 'ARin1 Rea"1 Se ect:1 A""1 8in 8out1 PCin1 7in1 @'FC 'DRout1 IRin PCout1 'ARin1 Rea"1 Se ect:1 A""1 8in 8out1 PCin1 7in R6out1 7in1 @'FC 'DRout1 Se ect71 A""1 8in 8out1 R6in1 En"

,dd the contents o! #e#ory location /UM to register R)

6$ =$ 9$ :$ A$ C$ D$ E$ G$

PCout1 'ARin1 Rea"1 Se ect:1 A""1 8in 8out1 PCin1 7in1 @'FC 'DRout1 IRin PCout1 'ARin1 Rea"1 Se ect:1 A""1 8in 8out1 PCin1 @'FC 'DRout1 'ARin1 Rea" R6out1 7in1 @'FC 'DRout1 Se ectF71 A""1 8in 8out1 R6in1 En"

,dd the contents o! the #e#ory location whose address is at the #e#ory location /UM to register R)

6$ =$ 9$ :$ A$ C$ D$ E$ G$ 65$

PCout1 'ARin1 Rea"1 Se ect:1 A""1 8in 8out1 PCin1 7in1 @'FC 'DRout1 IRin PCout1 'ARin1 Rea"1 Se ect:1 A""1 8in 8out1 PCin1 @'FC 'DRout1 'ARin1 Rea"1 @'FC 'DRout1 'ARin1 Rea" R6out1 7in1 @'FC 'DRout1 Se ectF71 A""1 8in 8out1 R6in1 En"

BR,/CB I/.TRUCTI$/ Rep aces the contents o! PC with the *ranch tar%et a""ress$
Usua # o*taine" *# a""in% an o!!set H1 %i)en in the *ranch instruction1 to the up"ate" )a ue o! PC$ O!!set is the "i!!erence *etween the *ranch tar%et a""ress an" the a""ress i&&e"iate # !o owin% the *ranch instruction$
E$%$ i! *ranch instruction is at ocation =555 an" *ranch tar%et a""ress is =5A51 the )a ue o! o!!set is :C

6$ =$ 9$

:$ A$

THE FETCH PHASE PCout1 'ARin 1 Rea"1 Se ect:1 A""1 8in 8out1 PCin1 7in1 @'FC 'DRout 1 IRin END OF FETCH PHASE The o!!set )a ue is extracte" !ro& the IR *# the instruction "eco"in% circuit$ O!!setF!ie "Fo!FIRout1 Se ectF71 A""1 8in 8out1 PCin1 En"

Conditional Branch .tate#ent


@e nee" to chec. the status o! the con"ition co"es *e!ore oa"in% a new a""ress into the PC For exa&p e 1 !or a BranchFonFne%ati)e ,BranchI56$ PCout1 'ARin 1 Rea"1 Se ect:1 A""1 8in =$ 8out1 PCin1 7in1 @'FC 9$ 'DRout 1 IRin :$ O!!setF!ie "Fo!FIRout1 Se ectF71 A""1 8in 1 I! NJ5 then En" A$ 8out1 PCin1 En" Thus i! NJ51 the processor returns to step 6 i&&e"iate # a!ter step :$ I! NJ61 step A is per!or&e" to oa" a new )a ue into PC1 thus per!or&in% the *ranch operation$

Multiple Bus $rganisation

Sin% e Bus s#ste&s ha)e ;en%th# contro se0uences


On # one "ata ite& can *e trans!erre" at a ti&e So ution is to pro)i"e &u tip e interna paths$

Three Bus Organisation of the Datapath


0us ( 0us 0 !ncrementer PC )egister file Constant 'U/ ( (1U 0 !nstruction decoder !) '") '() 'emory 3us data lines (ddress lines ) 0us C

A %enera purpose re%isters are co&*ine" into a sin% e * oc. ca e" the register file which has 9 ports
Two o3p1 a owin% the contents o! two "i!!erent re%isters to *e accesse" si&u taneous # an" ha)e their contents p ace" on *uses A an" B Thir" a ows the "ata on *us C to *e oa"e" on a thir" re%ister "urin% the sa&e c oc. c#c e$

Buses A an" B are use" to trans!er the source operan"s to A an" B I3p o! A;U$ The resu t is trans!erre" to the "estination o)er *us C$ The A;U can a so pass one o! the I3p unchan%e" to o3p C *# usin% si%na s RJA or RJB$ No nee" !or the re%isters 7 an" 8$ Incre&enter unit a""s : to PC1 e i&inatin% the nee" to "o so in A;U$

Exa#ple C ,00 R(3 RD3 RE 6$ =$ 9$ :$ A$ PCout1 RJB1 'ARin 1 Rea"1 IncPC @'FC 'DRoutB1 RJB1 IRin R:outA1 RAoutB1 Se ectFA1 A""1 RCin1 En" Contents o! PC are passe" throu%h A;U an" oa"e" into 'AR to start a 'e&or# Rea"$ The PC is then incre&ente" *# : an" the incre&ente" )a ue is oa"e" into PC$ The processor waits !or 'FC an" oa"s the "ata recei)e" into 'DR The contents o! 'DR are trans!erre" to IR Execution Phase

C$ D$ E$

Control Unit
The 'asic tas% o! the control unitC !or each instruction the contro unit causes the CPU to %o throu%h a se0uence o! contro steps2 in each contro step the contro unit issues a set o! si%na s which cause the correspon"in% &icrooperations to *e execute"$ The contro unit is "ri)en *# the processor c oc.$ The si%na s to *e %enerate" at a certain &o&ent "epen" on4 the actua step to *e execute"2 the con"ition an" status ! a%s o! the processor2 the actua instruction execute"2 externa si%na s recei)e" on the s#ste& *us ,e$%$ interrupt si%na s-$

Control Unit

Control Unit 0esign To execute instructions1 the processor &ust ha)e so&e &eans o! %eneratin% the contro si%na s nee"e" in proper se0uence$ Techni0ues !or i&p e&entation o! the contro unit4

Har"wire" contro 'icropro%ra&&e" contro

HARDWIRED CONTROL UNIT

Bardwired Control Units


In har"wire" contro units1 contro si%na s e&anate !ro& * oc.s o! "i%ita o%ic co&ponents$ These si%na s "irect a o! the "ata an" instruction tra!!ic to appropriate parts o! the s#ste&$ @e nee" a specia "i%ita circuit that uses1 as inputs1 the *its !ro& the opco"e !ie " in our instructions1 *its !ro& the ! a% ,or status- re%ister1 si%na s !ro& the *us1 an" si%na s !ro& the c oc.$ It shou " pro"uce1 as outputs1 the contro si%na s to "ri)e the )arious co&ponents in the co&puter

Bardwired Control Units


A o! the contro ines are ph#sica # connecte" to the actua &achine instructions$ The instructions are "i)i"e" up into !ie "s1 an" "i!!erent *its in the instruction are co&*ine" throu%h )arious "i%ita o%ic co&ponents to "ri)e the contro ines$

Control Unit Organisation

Hard ired Control Unit


The counter .eeps trac. o! the contro steps The re0uire" contro si%na s are "eter&ine" *#
Contents o! contro step counter Contents o! Instruction Re%ister Contents o! con"ition co"e ! a%s Externa input si%na s1 i.e 'FC an" interrupt re0uests$

Separation of De!oding " En!oding #$n!tions

#$n!tioning
The step "eco"er pro)i"es a separate si%na ine !or each step or ti&e s ot in the contro se0uence$ O3p o! the instruction "eco"er consists o! a separate ine !or each &achine instruction$ For an# instruction oa"e" in the IR1 one o! the o3p ines INS6 throu%h INS& is set to 6 an" a other are set to 5$ The I3p si%na s to the enco"er * oc. are co&*ine" to %enerate the in"i)i"ua contro si%na s 7in1 PCout1 ADD1 END etc$ I! RunJ61 the counter is incre&ente" *# one at en" o! e)er# c oc. c#c e an" i! RunJ51 the counter stops countin%$
Nee"e" whene)er @'FC si%na is issue"1 to cause the processor to wait !or rep # !ro& &e&or#$

E%a&ple ' (in


Zin = ! " 6 ADD " 4 BR " # #
Generation of signal Zin:
first step of all instructions (fetch instruction) step 6 of ADD with register addressing step 4 of BR step 6 of ADD with registerindirect addressing

E%a&ple ' END


E/0 * T<",00 F TD"BR F 5TD"/FT("/6BR/ F G""

Control H/

as a State )a!*ine

The contro h3w can *e )isua i(e" as a state &achine that chan%es !ro& one state to another in e)er# c oc. c#c e "epen"in% on the contents o! the IR1 the con"ition co"es an" the externa I3p$ The o3p o! the state &achine are the contro si%na s$

+ros and Cons


The a")anta%e o! har"wire" contro is that it is )er# !ast$ The "isa")anta%e is that the instruction set an" the contro o%ic are "irect # tie" to%ether *# specia circuits that are co&p ex an" "i!!icu t to "esi%n or &o"i!#$ I! so&eone "esi%ns a har"wire" co&puter an" ater "eci"es to exten" the instruction set the ph#sica co&ponents in the co&puter &ust *e chan%e"$ This is prohi*iti)e # expensi)e1 *ecause not on # &ust new chips *e !a*ricate" *ut a so the o " ones &ust e ocate" an" rep ace"$

Blo!, Diagra& of a !o&plete +ro!essor