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Topics Under Review How a processor executes instructions The interna !unctiona units o! a processor an" how the# are interconnecte"$ Har"ware !or %eneratin% interna contro si%na s The &icropro%ra&&in% approach 'icropro%ra& or%ani(ation
Processing Unit The CPU executes a sequence of instructions. The execution of an instruction is organized as an instruction cycle: it is performed as a succession of several steps; Each step is executed as a set of several microoperations.
Instruction Execution
The processor !etches one instruction at a ti&e an" per!or&s the operations speci!ie"$ Instructions are !etche" !ro& successi)e &e&or# ocations unti a *ranch or a +u&p instruction is encountere"$ The Pro%ra& Counter ,PC- re%ister .eeps trac. o! the a""ress o! the &e&or# ocation !ro& where the next instruction is to *e !etche"$ PC is up"ate" a!ter each instruction is !etche"$ One instruct &a# occup# &ore than one wor" / re0uirin% &ore than one !etch operation$
"ecode Cycle
No
!f #perand$s% required
Yes
etch #perand$s% Execute !nstruction &top #perand etch Cycle
Execute Cycle
PC (ddress 1ines 'emory 0us "ata 1ines Constant 2alue &elect 'U/ '() '") *
!) ), . . . )$n-.% TE'P
( (1U
Carry !n +
Instruction Execution
The tas4 performed 3y any microoperation falls in one of the follo5ing categories:
Transfer data from one register to another; Transfer data from a register to an external interface $system 3us%; Transfer data from an external interface to a register; Perform an arithmetic or logic operation6 using registers for input and output.
Control Signals
The CPU executes an instruction as a se uence o! control steps" In each control step one or several #icrooperations are executed" $ne cloc% pulse triggers the activities corresponding to one control step & !or each cloc% pulse the control unit generates the control signals corresponding to the #icrooperations to 'e executed in the respective control step
Riout Yin
/ !nternal Processor 0us
7 7 7 7
Constant Select
'U/ (
0 (1U
Zin
/ Z /
Zout
Control Signals
In or"er to a ow the execution o! a microoperation1 one or se)era control signals ha)e to *e issue"2 the# a ow the correspon"in% "ata trans!er an"3or co&putation to *e per!or&e"$ Exa&p es4 a- si%na s !or trans!errin% content o! re%ister R5 to R64 R5out1 R6in *- si%na s !or a""in% content o! 7 to that o! R5 ,resu t in 8-4 R5out1 A""1 8in c- si%na s !or rea"in% a &e&or# ocation2 a""ress in R94 R9out1 'ARin1 Rea"
Register Trans!ers Instruction execution in)o )es a series o! steps in which "ata are trans!erre" !ro& one re%ister to another$ For each re%ister1 two contro si%na s are use" to p ace the contents o! the re%ister on to the *us or or to oa" the "ata on the *us into the re%isters$
Re%ister Trans!er
Ti&in% o! a processor operations an" "ata trans!ers within the processor "e!ine" *# the processor c oc.$ Contro si%na s are asserte" at the *e%innin% o! the c oc. c#c e$ The re%isters are &a"e o! e"%e tri%%ere" ! ip ! ops$ Exa&p e R: R6
Per!or#ing an , or + operation
A;U has no interna stora%e$ One I3p co&es !ro& the O3p o! 'ux an" the other co&es "irect # !ro& the *us$ The resu ts are te&porari # store" in 8$ The contro si%na s are acti)ate" !or the "uration o! the c oc. c#c e correspon"in% to the step1 a other si%na s are inacti)e$ R9 R6 < R=
R6OUT 1 7IN R=OUT 1 SE;ECT 7 1 ADD 1 8IN 8OUT 1 R9IN
MDR
/ '")inE
/ '")in
'AR>R6? Start rea" on &e&or# *us @ait !or 'e&or# Function Co&p ete" ,'FC- !ro& &e&or# ;oa" 'DR !ro& *us R=>'DR?
R6out1 'ARin1 Rea" 'DRinE1 @'FC ,wait !or 'FC'DRout1R=in
Co&p ete Instruction Execution Exa&p e ADD R61 '>R9? A""s the contents o! the &e&or# ocation pointe" to *# R9 to re%ister R6$
Fetch the instruction Fetch the !irst operan" ,the contents o! the &e&or# ocation pointe" to *# R9 Per!or& the a""ition$ ;oa" the resu t into R6
PC (ddress 1ines 'emory 0us "ata 1ines Constant 2alue &elect 'U/ '() '") *
!) ), . . . )$n-.% TE'P
( (1U
Carry !n +
9" ;"
1igure out what the instruction should do and set control circuitry !or steps (8<" <" =" >"
)?" result is trans!erred to R)3 End causes a goto step ) 7$UT3 R)I/3 E/0
Pro'le#
Assu&in% a &e&or# rea" or write operation ta.es the sa&e ti&e as one interna processor step an" that *oth the processor an" the &e&or# are contro e" *# the sa&e c oc.$ Esti&ate execution ti&eB @hat wi *e the execution ti&e i! the &e&or# access ti&e is e0ua to twice the processor c oc. perio"$
< cloc%s
> cloc%s
Assu&in% that each instruction consists o! two wor"s$ The !irst wor" speci!ies the operation an" the secon" wor" contains the nu&*er NU'$ A so assu&e a sin% e *us structure as "iscusse"$ @rite the se0uence o! contro steps re0uire" !or4 a- A"" the nu&*er NU' to re%ister R6 *- A"" the contents o! &e&or# ocation NU' to re%ister R6 c- A"" the contents o! the &e&or# ocation whose a""ress is at the &e&or# ocation NU' to re%ister R6
6$ =$ 9$ :$ A$ C$ D$ E$
PCout1 'ARin1 Rea"1 Se ect:1 A""1 8in 8out1 PCin1 7in1 @'FC 'DRout1 IRin PCout1 'ARin1 Rea"1 Se ect:1 A""1 8in 8out1 PCin1 7in R6out1 7in1 @'FC 'DRout1 Se ect71 A""1 8in 8out1 R6in1 En"
6$ =$ 9$ :$ A$ C$ D$ E$ G$
PCout1 'ARin1 Rea"1 Se ect:1 A""1 8in 8out1 PCin1 7in1 @'FC 'DRout1 IRin PCout1 'ARin1 Rea"1 Se ect:1 A""1 8in 8out1 PCin1 @'FC 'DRout1 'ARin1 Rea" R6out1 7in1 @'FC 'DRout1 Se ectF71 A""1 8in 8out1 R6in1 En"
,dd the contents o! the #e#ory location whose address is at the #e#ory location /UM to register R)
6$ =$ 9$ :$ A$ C$ D$ E$ G$ 65$
PCout1 'ARin1 Rea"1 Se ect:1 A""1 8in 8out1 PCin1 7in1 @'FC 'DRout1 IRin PCout1 'ARin1 Rea"1 Se ect:1 A""1 8in 8out1 PCin1 @'FC 'DRout1 'ARin1 Rea"1 @'FC 'DRout1 'ARin1 Rea" R6out1 7in1 @'FC 'DRout1 Se ectF71 A""1 8in 8out1 R6in1 En"
BR,/CB I/.TRUCTI$/ Rep aces the contents o! PC with the *ranch tar%et a""ress$
Usua # o*taine" *# a""in% an o!!set H1 %i)en in the *ranch instruction1 to the up"ate" )a ue o! PC$ O!!set is the "i!!erence *etween the *ranch tar%et a""ress an" the a""ress i&&e"iate # !o owin% the *ranch instruction$
E$%$ i! *ranch instruction is at ocation =555 an" *ranch tar%et a""ress is =5A51 the )a ue o! o!!set is :C
6$ =$ 9$
:$ A$
THE FETCH PHASE PCout1 'ARin 1 Rea"1 Se ect:1 A""1 8in 8out1 PCin1 7in1 @'FC 'DRout 1 IRin END OF FETCH PHASE The o!!set )a ue is extracte" !ro& the IR *# the instruction "eco"in% circuit$ O!!setF!ie "Fo!FIRout1 Se ectF71 A""1 8in 8out1 PCin1 En"
A %enera purpose re%isters are co&*ine" into a sin% e * oc. ca e" the register file which has 9 ports
Two o3p1 a owin% the contents o! two "i!!erent re%isters to *e accesse" si&u taneous # an" ha)e their contents p ace" on *uses A an" B Thir" a ows the "ata on *us C to *e oa"e" on a thir" re%ister "urin% the sa&e c oc. c#c e$
Buses A an" B are use" to trans!er the source operan"s to A an" B I3p o! A;U$ The resu t is trans!erre" to the "estination o)er *us C$ The A;U can a so pass one o! the I3p unchan%e" to o3p C *# usin% si%na s RJA or RJB$ No nee" !or the re%isters 7 an" 8$ Incre&enter unit a""s : to PC1 e i&inatin% the nee" to "o so in A;U$
Exa#ple C ,00 R(3 RD3 RE 6$ =$ 9$ :$ A$ PCout1 RJB1 'ARin 1 Rea"1 IncPC @'FC 'DRoutB1 RJB1 IRin R:outA1 RAoutB1 Se ectFA1 A""1 RCin1 En" Contents o! PC are passe" throu%h A;U an" oa"e" into 'AR to start a 'e&or# Rea"$ The PC is then incre&ente" *# : an" the incre&ente" )a ue is oa"e" into PC$ The processor waits !or 'FC an" oa"s the "ata recei)e" into 'DR The contents o! 'DR are trans!erre" to IR Execution Phase
C$ D$ E$
Control Unit
The 'asic tas% o! the control unitC !or each instruction the contro unit causes the CPU to %o throu%h a se0uence o! contro steps2 in each contro step the contro unit issues a set o! si%na s which cause the correspon"in% &icrooperations to *e execute"$ The contro unit is "ri)en *# the processor c oc.$ The si%na s to *e %enerate" at a certain &o&ent "epen" on4 the actua step to *e execute"2 the con"ition an" status ! a%s o! the processor2 the actua instruction execute"2 externa si%na s recei)e" on the s#ste& *us ,e$%$ interrupt si%na s-$
Control Unit
Control Unit 0esign To execute instructions1 the processor &ust ha)e so&e &eans o! %eneratin% the contro si%na s nee"e" in proper se0uence$ Techni0ues !or i&p e&entation o! the contro unit4
#$n!tioning
The step "eco"er pro)i"es a separate si%na ine !or each step or ti&e s ot in the contro se0uence$ O3p o! the instruction "eco"er consists o! a separate ine !or each &achine instruction$ For an# instruction oa"e" in the IR1 one o! the o3p ines INS6 throu%h INS& is set to 6 an" a other are set to 5$ The I3p si%na s to the enco"er * oc. are co&*ine" to %enerate the in"i)i"ua contro si%na s 7in1 PCout1 ADD1 END etc$ I! RunJ61 the counter is incre&ente" *# one at en" o! e)er# c oc. c#c e an" i! RunJ51 the counter stops countin%$
Nee"e" whene)er @'FC si%na is issue"1 to cause the processor to wait !or rep # !ro& &e&or#$
Control H/
as a State )a!*ine
The contro h3w can *e )isua i(e" as a state &achine that chan%es !ro& one state to another in e)er# c oc. c#c e "epen"in% on the contents o! the IR1 the con"ition co"es an" the externa I3p$ The o3p o! the state &achine are the contro si%na s$