MICROPROGRAMMED CONTROL

Overview
The control unit initiates the sequences of microoperations. Every system has a finite number of microinstruction types. Complexity of the digital system is derived from the no. of sequences of microoperations that are performed. The control function which specifies a microoperation is a binary variable. n a bus organised system! the control signals that specify microoperations are groups of bits that select the paths in multiplexers! decoders and "#$ c%ts.

Overview
The control variables at any given time can be represented by a string of &s and 's called a control word. Control words can be programmed to perform various operations on system components. " control unit whose binary control variables are stored in memory is called a Microprogrammed Control (nit.

Terminology
Microprogram
Program stored in memory that generates all the control signals required to execute the instruction set correctly Consists of microinstructions

Microinstruction
Contains a control word and a sequencing word
Control Word - All the control information required for one clock cycle Sequencing Word - Information needed to decide the next microinstruction address

Vocabulary to write a micro rogram

Terminology
Control Memory (CM)
Storage in the microprogrammed control unit to store the microprogram ROM

Writeable Control Memory

CM whose contents can be modified
Allows the microprogram can be changed Instruction set can be changed or modified

ynamic Microprogramming
Computer system whose control unit is implemented with a microprogram in Writable CM Microprogram can be changed by a systems programmer or a user

Microprogrammed Control Organisation

!xternal In ut
!e"t Address #enerator (Se$uencer) Control Word Control Address Register Control Memory (ROM) Control ata Register

"ext Address Information

Microprogram e!"encer
The )ext "ddress *enerator is also called the Microprogram sequencer. +etermines the address sequence to be read from control memory Many ways of specifying addresses depending on sequencer inputs. ,unctions of sequencer include
ncrementing control register by one $oad an address from control memory into C"Transfer an external address $oad an initial address to start the control operations.

Control Address Register

.pecifies the address of microinstructions "fter execution of the operations specified in the microinstruction! the control must determine the next microinstruction/s address. The address of next microinstruction is a function of some bits of current instruction and external 0p. 1hile the current microinstruction is being executed! the next address is generated in )"* and is transferred to C"- to read the next microinstructions. Thus a microinstruction contains
bits for initiating microoperations in the data processor part and bits that determine the address sequence for the control memory.

Control Memory
The control memory holds a fixed microprogram. The microprogram consists of microinstructions that specify various control signals for execution of register microoperations. Each machine instruction in main memory initiates a series of microinstructions in control memory. These microinstructions generate the microoperations to
,etch the instruction from main memory Evaluate the effective address Execute the operation specified by the instruction -eturn control to fetch phase to repeat the cycle for next instruction.

Control Data Register

2olds the present microinstruction while the next address is computed and read from memory. "lso called 3ipeline -egister. "llows execution of microinstruction simultaneously with generation of next instruction. This necessitates a two4phase cloc%! one cloc% applied to the address register and the other to the data register each.

An example Microinstruction

Assuming Select-Y to be represented by Select=0 and Select-4 by Select=1

MDR out

MARin

Micro instruction 1 2 3 4 5 6 7

WMFC 0 1 0 0 1 0 0

Select

PCout

Read

R1out

R3out 0 0 0 1 0 0 0

PCin

Add

IRin

0 1 0 0 0 0 0

1 0 0 0 0 0 0

1 0 0 1 0 0 0

1 0 0 1 0 0 0

0 0 1 0 0 1 0

0 0 1 0 0 0 0

0 1 0 0 1 0 0

1 0 0 0 0 0 0

1 0 0 0 0 1 0

1 0 0 0 0 1 0

Zout

0 1 0 0 0 0 1

0 0 0 0 1 0 0

R1in

0 0 0 0 0 0 1

End 0 0 0 0 0 0 1

Yin

Zin

Advantages o# Microprogrammed Control

5nce we have established the hardware configuration! no further hardware or wiring change is required. "ny new or different control sequence can be implemented by specifying a different set of microinstruction. Thus the only thing needed to change is the microprogram in the memory.

"$ro"tines
Microinstructions are stored in control memory in groups! each group specifying a routine. .ubroutines are 3rograms used by other routines to accomplish a particular tas%. " subroutine can be called from any point within the main body of the microprogram. .ame subroutine can be called from many microprograms. 2elps in reducing si6e of microprograms. )eed to store the return address during the subroutine call. ncremented o0p from C"- goes to a .ubroutine -egister .7and execution branches to beginning of subroutine. .7- becomes source of return address.

Instr"ction %ormat
15 14 11 10 0

5pcode

"ddress

.ymbol "++ 7-")C2 .T5-E E>C2")*E

5pcode '''' '''& ''&' ''&&

+escription "C "C 8 M 9 E" : f ;"C<'= then ;3C E" = M 9 E" : "C "C M 9 E" :! M 9 E" : "C

EA is the effective Address

Address e!"encing
When computer is switched on !A" is loaded with an initial address pointing to #irst microinstruction that acti$ates the #etch routine% &etch routine is se'uenced by incrementing the !A" through the rest o# microinstructions% At end o# #etch routine the instruction is in ("% )he address o# operand needs to be calculated% *its in machine instruction speci#y $arious addressing modes% Mode bits decide the the conditions which chose the branch microinstruction which is used to calculate e##ecti$e address%

Address e!"encing
At end o# address calculation routine the address o# operand is in MA"% Microinstructions to execute the instruction #etched #rom memory need to be generated% Microoperation steps generated in process registers depend on opcode% +ach instruction has its own microprogram routine stored in a gi$en location o# control memory%
)rans#ormation #rom the instruction code bits to an address in control memory where the routine is located is called mapping process%

Address e!"encing
A mapping procedure is a rule that trans#orms the instruction code into a control memory address% ,nce the re'uired routine is reached the microinstruction that execute the instruction may be se'uenced by incrementing the !A"% Microprograms that use subroutines re'uire an external register #or storing the return address% At end o# instruction execution control returns to #etch routine by executing an unconditional branch microinstruction to #irst address o# #etch routine%

Address e!"encing
Address se'uencing capabilities re'uired in control memory are
Incrementing of the control address register #CA$% &nconditional and conditional branches A ma ing rocess from the bits of the machine instr to an address for C' A facility for subroutine call and return

Selection of Address for Control Memory

&RANC'ING (

PECIAL &IT

The status conditions are special bits in the system that provide parameter information such as the carry4out of an adder! the sign bit of a number! the mode bits of an instruction! and input or output status conditions. nformation in these bits can be tested and actions initiated based on their condition? whether their value is & or '. The status bits! together with the field in the microinstruction that specifies a branch address! control the conditional branch decisions generated in the branch logic.

&RANC'ING LOGIC
The simplest way is to test the specified condition and branch to the indicated address if the condition is met@ otherwise! the address register is incremented. This can be implemented with a multiplexer.
.uppose that there are eight status bit conditions in the system. Three bits in the microinstruction are used to specify any one of eight status bit conditions. These three bits provide the selection variables for the multiplexer. f the selected status bit is in the & state! the output of the multiplexer is &@ otherwise! it is '. " & output in the multiplexer generates a control signal to transfer the branch address from the microinstruction into the control address register. " ' output in the multiplexer causes the address register to be incremented.

)NCONDITIONAL &RANC'ING
"n unconditional branch microinstruction can be implemented by loading the branch address from control memory into the control address register. This can be accomplished by fixing the value of one status bit at the input of the multiplexer! so it is always equal to &. " reference to this bit by the status bit select lines from control memory causes the branch address to be loaded into the control address register unconditionally.

MAPPING
" special type of branch exists when a microinstruction specifies a branch to the first word in control memory where a microprogram routine for an instruction is located. The status bits for this type of branch are the bits in the operation code part of the instruction.

Mapping o# Instr"ctions to Microro"tines

4 bits that can specify upto 16 distinct instructions

7 bits that can specify upto 128 distinct words in the control memory

)&RO)TINE
" subroutine can be called from any point within the main body of the microprogram. Microprograms that use subroutines must have a provision for storing the return address during a subroutine call and restoring the address during a subroutine return. This may be accomplished by placing the incremented output from the control address register into a subroutine register and branching to the beginning of the subroutine. The subroutine register can then become the source for transferring the address for the return to the main routine. The best way to structure a register file that stores addresses for subroutines is to organi6e the registers in a last4in! first4out ;$ ,5= stac%.

 Two Memories

Comp"ter '* Con#ig"ration

M%& '( AR Address '( -C ( ( Memory )(*+ " ',

Main memory Control Memory 4 registers associated to processor unit PC ! ccumulator C "! 2 registers associated to C#
M%&

C !
(

, S/R

, CAR

'.

$ubroutine !egister $%! Transfer of info in registers in processor done through mu& '$# performs microop with data from C and "! and places result in C

Control memory ')+ " )( Control unit

Arithmetic logic and shift unit '. AC (

Memory recei(es address from ! and "ata written to or read from memory goes to "!

Instr"ction %ormat
15 14 11 10 0

5pcode

"ddress

.ymbol "++ 7-")C2 .T5-E E>C2")*E

5pcode '''' '''& ''&' ''&&

+escription "C "C 8 M 9 E" : f ;"C<'= then ;3C E" = M 9 E" : "C "C M 9 E" :! M 9 E" : "C

EA is the effective Address

Microinstr"ction
MICROINSTRUCTION ORMAT
A ,& A ,B A ,A B C+ B 7C "+

1! "! # $ Microo%er&tion field ' s%ecify microo%er&tions C( $ Condition for )r&nchin* ' select st&t+s )it conditions ,R $ ,r&nch field ' s%ecify the ty%e of )r&nch to )e +sed A( $ Address field ' cont&in & )r&nch &ddress

Microoperations %ield + , + - . $its

+ivided into A fields of A bits each. A bits in each field specify C distinct microoperations. TotalDB& 5ne microinstruction can chose maximum A microoperations. " field uses code ''' to show no4operation. ,or example +- M9"-:! 3C3C8& .pecified as ''' &'' &'& B or more conflicting microops cannot be specified simultaneously eg. '&' ''& '''

0' ((( ((' ('( ('' '(( '(' ''( '''

Microoperation !one AC 2 AC 3 R AC 2 ( AC 2 AC 3 ' AC 2 R AR 2 R((4'() AR 2 -C M9AR: 2 R

Symbol !OA C5RAC I!CAC R8AC R8AR -C8AR WRI8;

0) ((( ((' ('( ('' '(( '(' ''( '''

Microoperation !one AC 2 AC 4 R AC 2 AC R AC 2 AC R R 2 M9AR: R 2 AC R2 R3' R((4'() 2 -C

Symbol !OS%/ OR A! R;A AC8 R I!C R -C8 R

01 ((( ((' ('( ('' '(( '(' ''( '''

Microoperation !one AC 2 AC R AC 2 AC6 AC 2 shl AC AC 2 shr AC -C 2 -C 3 ' -C 2 AR Reser<ed

Symbol !O&OR COM S75 S7R I!C-C AR8-C

Condition %ield

/ &its

C+ D '' always finds condition as T-(E. 1hen used in conjunction with 7-;7ranch= field it provides an unconditional branch operation. ndirect bit is available from bit &E of +- after an instruction is read from memory. .ign bit of "C provides next status bit. Fero value F is a binary variable whose value is equal to & if all bits in "C are aero
C (( (' '( '' Condition Always = ' R('.) AC('.) AC = ( Symbol % I S > Comments %nconditional branch Indirect address bit Sign bit of AC >ero <alue in AC

&ranc0 %ield / &its

-sed in con.unction with address #ield A/ to chose the address o# next microinstruction% 0M1 and !A22 are similar except that a !A22 microinstruction stores the return address in S*"% )he .ump and call operations depend on $alue o# !/ #ield% (# status bit condition speci#ied in !/ is 1 the next address in A/ is trans#erred to !A" otherwise !A" is incremented by 1% 3alue o# 10 in *" causes a return #rom subroutine% )his causes the trans#er o# return address #rom S*" to !A"% *"=11 causes mapping #rom operation code #ield o# the instruction to an address #or !A"%

/R (( (' '( ''

Symbol ?MCA55 R;8 MA-

0unction CAR 2 A if condition = ' CAR 2 CAR 3 ' if condition = ( CAR 2 A @ S/R 2 CAR 3 ' if condition = ' CAR 2 CAR 3 ' if condition = ( CAR 2 S/R (Return from subroutine) CAR()4.) 2 R(''4'*)@ CAR((@'@,) 2 (

Selection of Address for Control Memory

Microprogram e!"encer %or a Control Memory

Microprogram e!"encer
7asic components of microprogrammed control unit
Control memory C%t that selects the next address G microprogram sequencer

M. presents an address to the control memory so that a microinstruction may be read and executed. " typical sequencer has a subroutine register stac% about H4I levels deep so that a no. of subroutines can be active simultaneously.

Ne,t Address Logic

The next address logic of the sequencer determines the specific address source to be loaded into the C"-. The choice of the address source is guided by the next address information bits that the sequencer receives from the current microinstruction.

Ne,t Microinstr"ction Address Logic

Condition 1 &ranc0 Logic

"etermines the type of operations a(ailable in the se)uencer unit*

$+ and $1 select one of the src addresses for C ! ' enables the load ,-p in $%!