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Chapter Objectives
Microprocessor Fundamentals
Major Components of a Computer MPU Model Length of Instructions Memory Map
Memory Devices
Address Decoding
Chapter Objectives
The 8086/8088 Microprocessors, Interrupts and DMA
The 8088 Microprocessor in Circuit
Interrupts
SECTION 1:
MICROPROCESSOR FUNDAMENTALS
MPU Fundamentals
For Simplicity look at a simple model of an MPU
8-bit 64K address space Intel style interface
General Registers
Instruction Register
Accumulator
Temp Reg
Instruction Decoder
C Z N
ALU
RESET
Control Unit
Clock
IOR#
IOW#
MEMR#
MEMW#
INTR
INTA#
MPU
General Registers
Small set of internal registers - temporary data storage CU ensures that data from the correct register is presented to the ALU CU ensures that data is written back to correct register Accumulator usually holds ALU result
Stack Pointer
STACK: Part of memory where program data can be stored by a simple PUSH operation Restore data by a POP Stack is in main memory and is defined by the program Stack Pointer (SP) keeps track of the next location available on the Stack Organised as a FILO Buffer
Stack Exercise
At the start of the following sequence the Stack Pointer has the value C000h. The following code is executed PUSH AL ; Push 8 bit accumulator data PUSH PSW ; Push 8 bit flags register What is the value of the SP at this point? The following instructions are executed without any further stack activity in the meantime POP POP PSW AL ; Restore 8 bit flags register ; Restore 8 bit accumulator data
What is the value of the SP at this point? Note how the POP order is the reverse of the PUSH order.
Interrupt Control
HLDA#
Reset
HOLD
DMA Control
Fetch-Decode-Execute
FETCH
DECODE
EXECUTE
Fetch-Decode-Execute (Memory)
Address Bus Address Bus Address Bus
MPU
Program Memory
MPU
Program Memory
MPU
Program Memory
Data Bus
Data Bus
Data Bus
Instructiom Op Code is read into the IR register via the data bus for decoding
Instruction is executed
Memory Map
16 Address Bus: 16 bits, 2 = 64K locations. Data Bus: 8 bits (1 byte)
FFFFh
0000h 1 byte
Data D0..D7
Data D0..D7
OE Chip Enable
CE
OE WE
Read Cycle
Processor puts out address on the Address Bus, e.g. 5 0000 0000 0000 0101 (A) Address RAM
8K bytes
Data D0..D7 Processor reads the contents of the data bus (C)
OE WE
Address Bus
Program Address
Data Address
RD#
Data Bus
OpCode
Operand
Valid Data
Write Cycle
Processor puts out address on the Address Bus, e.g. 9 0000 0000 0000 1001 (A) Address RAM
8K bytes
Data D0..D7 Processor writes the data to the RAM via the data bus (C)
OE WE
Address Bus
Program Address
Data Address
WR#
Data Bus
Write Data
Valid Data
I/O Instructions
Separate I/O instructions cause the IOR# or IOW# signals to be asserted
MOV AL, (400Fh) ; instruction provides 16-bit address IN AL, 2Ch ; instruction provides an 8-bit address
Some processors only support a single address space - I/O devices are decoded in the memory map
Memory manipulations can be performed directly on I/O locations No need for IOR# and IOW# pins
Smaller, faster instructions can be used for I/O Less Hardware decoding for I/O Easier to distinguish I/O accesses in assembly language Which mapping system is preferable? Why?
ROM1
RAM0
RAM1
How do you allow many memory devices to drive the same bus?
When Enable signal is active the output follows the input When the Enable signal is inactive the output of the buffer is effectively disconnected from the circuit When the output is in High Impedance other devices can drive the bus in question Bidirectional buffers (transceivers) are essentially two back-to back buffers
Input
Output
Enable#
Address Decoding
ADDRESS BUS
ROM1
RAM0
RAM1
CONTROL BUS
Address Decoding
Need external decoding hardware to ensure that only one device is accessed at any one time Simple techniques enable the Chip Enable of just one device, based on the address bus contents
Implement this system, consisting of 4 x (16K x 8) memories: ROM0 - 0000h - 3FFFh ROM1 - 4000h - 7FFFh RAM0 - 8000h - BFFFh RAM1 - C000h - FFFFh
RAM1
c000h bfffh
A15 /A15
RAM0
8000h 7fffh
A14 /A14
ROM1
4000h 3fffh
ROM0
0000h
/CS_ROM0
/CS_ROM1
/CS_RAM0
/CS_RAM1
ROM0
/OE
ROM1
/OE /WE
RAM0
/OE /WE
RAM1
D0..D7 A0..A13
D0..D7 A0..A13
D0..D7 A0..A13
D0..D7 A0..A13
D0..D7 A0..A13
A15 A14
/CE
/CE
/CE
/CE
138
E1 E2 E3
Outputs
Enable Inputs
RAM1
c000h bfffh 8000h 7fffh 4000h 3fffh A14 A B C
74AC138
/Y0 /Y1 /Y2 /Y3 /Y4 /CS_ROM0 /CS_ROM1 /CS_RAM0 /CS_RAM1 A15
/E1 /E2 E3
0000h
ROM0
/OE
ROM1
/OE /WE
RAM0
/OE /WE
RAM1
D0..D7 A0..A13
D0..D7 A0..A13
D0..D7 A0..A13
D0..D7 A0..A13
D0..D7 A0..A13
A15 A14
/CE
/CE
/CE
/CE
74AC138
A B C /Y0 /Y1 /Y2 /Y3 /Y4 /E1 /E2 E3 /Y5 /Y6 /Y7
Cascading 138s for More Complex Decoding 74138 generates a unique output for a given binary input You can cascade 138s for more complex and precise decoding Each stage has a propagation delay associated with it
May affect your timing budget
Cascaded 74138s
SEL0
0 1 2 3 4 5 6 7
A B C
SEL1
138
E1 E2 E3 Logic High SEL5 SEL7 A0 A1 A2 A B C A0 A1 A2 A B C
138
MEMR Logic High MEMW E1 E2 E3
0 1 2 3 4 5 6 7
IN A000 IN A001 IN A002 IN A003 IN A004 IN A005 IN A006 IN A007 Logic High
138
E1 E2 E3
0 1 2 3 4 5 6 7
Modern Decoding
Decoding in Motherboards is often done using Custom devices or PLDs Custom devices usually have 74138s as a Library part
(P)ROM
Data D0..D7
Address Input
Valid Data
MEMR# (= OE#)
CE#
Data Out
Valid Data
ta
MEMR# (= OE#)
CE#
Data Out
Valid Data
ta
SECTION 2
Memory Systems
Dynamic RAM (DRAM) Static RAM (SRAM) Cache Read-Only (ROM) Flash Memory EEPROM
Microprocessor
8086 8088 80186 80286 80386 80486 Pentium Pentium Pro Pentium II
I/O System
Printer Hard disk drive Mouse CD-ROM Drive Keyboard Monitor Scanner
Memory
Transient Program Area (TPA) 640Kb System Area 384 Kb Extended Memory System (XMS) over 4MB
Extended Memory
15M bytes in the 80286 31M bytes in the 80386SL/SLC 63M bytes in the 80386EX 4095M bytes in the 80386DX, 80486, and Pentium 64G bytes in the Pentium Pro and Pentium II
COMMAND.COM Device Drivers such as MOUSE.SYS MSDOS Programs IO.SYS Program DOS communications area BIOS communications area Interrupt Vectors
System Area
FFFFF F0000 E0000
Free Area
Hard disk controller ROM LAN controller ROM Video BIOS ROM Video RAM (Text area)
FFFF
I/O Space
Addresses I/O ports Up to 64K 8-bit devices
03F8
COM1 Floppy Disk Controller CGA Adapter LPT1 Hard disk Controller COM2 8255 (PIA) Timer (8253) Interrupt controller DMA Controller
03F0
03D0 0378 0320 02F8 0060 0040 0020 0000
Microprocessor
Data transfer between itself and memory or I/O system
Using data, address, and control buses
Why is it so important?
Keyboard
Printer
Computer System
Bus is a common group of wires for interconnection Address Bus: 16-bit for I/O and 20 to 36-bit for memory (20 for 8086)
Data Bus: 8 to 64-bit, the wider the bus, the more data can be transferred (16 for 8086)
Computer System
Control Bus: contains lines that selects the memory or I/O to perform a read or write operation
Four main control lines MRDC (memory read control) MWTC (memory write control) IORC (I/O read control) IOWC (I/O write control)
Register Types
Program Visible: used during application programs Program Invisible: not directly addressable, but used by system
e.g. ADD AL, AH; ADD DX, CX; ADD ECX, EBX
Instructions only affect the intended part of a register Later P versions support earlier version codes
All Intel, AMD and other advanced microprocessors are based on and are compatible with the original 8086/8 At Power Up and Reset time, Pentiums, Athlons etc all look like 8086 processors
Width of external address bus: 16b+4b=20b Some techniques to optimise the CPU performance when its executing programs Segment: Offset memory model Little-Endian Data Format
8086/8088 (1)
Original IBM PC used 8088 microprocessor 8088 is similar to the 8086, but it has an external 8b data bus & only 4B-deep queue
For cost reduction reasons
We can consider 8086 and 8088 together PC clones often used 8086 for better performance 8-bit bus reduces performance, but meant cheaper computers
8086/8088 (2)
Remember the Fetch-Decode-Execute cycle? Fetching from EXTERNAL MEMORY is SLOW The 8086/8 used an instruction queue to speed up performance While the processor is decoding and executing an instruction, its bus interface can be reading new instructions, since at that time the bus is not actually in use
8086/8088 MPU
8086/8088 (3)
8086/8088 consists of two internal units
The execution unit (EU) - executes the instructions The bus interface unit (BIU) - fetches instructions, reads operands and writes results
The 8086 has a 6B prefetch queue The 8088 has a 4B prefetch queue
Flags
BIU Elements
Instruction Queue: the next instructions or data can be fetched from memory while the processor is executing the current instruction
The memory interface is slower than the processor execution time so this speeds up overall performance
Segment Registers:
CS, DS, SS and ES are 16b registers Used with the 16b Base registers to generate the 20b address Allow the 8086/8088 to address 1MB of memory Changed under program control to point to different segments as a program executes
Instruction Pointer (IP) contains the Offset Address of the next instruction, the distance in bytes from the address given by the current CS register
8086/8 multiplex the address and data buses on the same pins
This saves pins but at a price:
Demultiplexing logic is needed to build up separate address and data buses to interface with RAMs and ROMs
MAXIMUM MODE GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND
20 21 1 40
MINIMUM MODE
8086
/RQ,/GT0 /RQ,/GT1 /LOCK /S2 /S1 /S0 QS0 QS1 /TEST READY RESET
MAXIMUM MODE GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND
20 21 1 40
MINIMUM MODE
GND A14 A13 A12 A11 A10 A9 A8 AD7
1 40
MAXIMUM MODE Vcc A15 A16,S3 A17,S4 A18,S5 A19,S6 high MN,/MX /RD
MINIMUM MODE
/SS0
8086
/RQ,/GT0 /RQ,/GT1 /LOCK /S2 /S1 /S0 QS0 QS1 /TEST READY RESET
AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND
20
8088
/RQ,/GT0 /RQ,/GT1 /LOCK /S2 /S1 /S0 QS0 QS1 /TEST READY
21
RESET
8086 CPU
MN/MX#
ADDR/DATA
ADDR/Data
RESET# Signal
The Active low RESET# signal puts the 8086/8 into a defined state Clears the flags register, segment registers etc. Sets the effective program address to FFFF0h (CS=0F000h, IP=0FFF0h) 8086/8 Programs always start at FFFF0H after Reset has been asserted and removed Continues into latest generation CPUs
Use of BHE#/A0(BLE#)
Byte-Wide addressing (8088) FFFFF FFFFE FFFFD FFFFC A19..A1 ODD Addresses (8086) FFFFF FFFFD FFFFB FFFF9 A19..A1 EVEN Addresses (8086) FFFFE FFFFC FFFFA FFFF8
D7:D0
Use of BHE#/BLE#
BHE# 0 0 1 A0/BLE# 0 1 0 Selection Whole word (16-bits) High byte to/from odd address Low byte to/from even address
No selection
ALE
Output of 74HC373
Microcomputer AddressBus
74HC373 or equivalent
In0:In7
Q0:Q7
ALE
LE OE# TriState Control signal, OE#, shown connected to GND for simplicity
T2
T3
T4
Address
Status
Valid Address
T2
T3
T4
Address
Status
Valid Address
T2
T3
Tw
T4
Address
Status
ALE 8284 RDY READY AD0..AD15 A0..A19 DT/R DEN /MRDC or /IORC
Address float Valid Data float
Valid Address
8086/8088 Summary
First Generation (introduced June 1978) One of the first 16b processors on the market 16b internal registers 16/8b external data bus
80186/80188
Evolution of 8086/8088 80186/80188 Increased instruction set On-chip system components (Clock generator, DMA, Interrupt, Timers) Unsuccessful in PCs Popular in embedded systems
Interrupts
Used to Halt the normal flow of instructions Exceptions can be due to Hardware or Software Hardware Interrupts are asynchronous to the processor Could be asserted by an external device requesting action, e.g. a port ready to transfer data Interrupts can be globally masked by the processors Interrupt Enable Flag (IE or I) IE is set by STI and reset by CLI (or equivalent)
NMI Example
Power Fail Monitor NMI
MPU INTR
I/O Device
Interrupts
Main Program
Interrupt Receiv ed
ISR
Complete Current Instruction PushFlags Register onto Stack Push Instruction Pointer onto Stack Clear Interrupt Enable Falg Trap to Start of ISR
Pop flags from the stack Pop Instruction Pointer from the stack Resume at restored IP address
Vectored Interrupt
Vectored Interrupt
DMA
FFFFF
1FFFF 1F000
Offset = F000
1000
00000
Addressing Modes
Data Addressing Modes Intel family supports 8 data addressing modes
Modes differ in the location of data and address calculations All modes involve physical address generation
Addressing Modes
Register Addressing: MOV CX, DX
Copy content of source register to destination register Source and destination must be of the same size
Addressing Modes
Direct Addressing: MOV CX, LIST
Move a byte or word between a memory location and a register Memory address, instead of data, appears in the instruction
Addressing Modes
Register Indirect Addressing: MOV AX, [BX]
Transfer data between a register and a memory location addressed by a register Sometimes need using special assembler directives BYTE PTR, WORD PTR, DWORD PTR, when size is not clear
FOR example MOV DWORD PTR [DI], 10H instead of MOV [DI], 10H
Addressing Modes
Base-plus-index Addressing: MOV [BX+DX], CL
Transfer data between a register and a memory location addressed by a base register and an index register
Addressing Modes
Base relative-plus-index Addressing: MOV AX, ARRAY[BX+DI]
Transfer data between a register and a memory location specified by a base and index register plus a displacement Another example is MOV AX, [BX+DI+4]
Addressing Modes
Scaled-index Addressing:
Not used by 8086 (used by 80386 and later processors)
Instruction Encoding
Assembler translates assembly code into machine language Machine language is the native binary code P understands
D W Opcode
MOD specifies addressing mode for instruction and whether displacement is present If MOD=11, then register addressing mode, else memory addressing mod In register addressing mode, R/M specifies a register In memory addressing mode, R/M selects a mode from table If D=1, data flow to REG from R/M, if D=0 data flow to R/M from REG
DEC subtracts one from a register or memory location CMP is a subtract that only changes the flag bits; this is normally followed by a conditional jump instruction
TEST is like CMP, but for bits zero flag Z=1 if bit is 0 and Z=0 if bit is 1