Memory interleaving

Lecture 09

COA by Athar Mohsin

 Main Memory
• The basic unit of memory is the binary digit “bit”. A bit contains a “0” or “1”.
• The most common definition of the word length of a computer is the number of bits
actually stored or retrieved in one memory access.
• Word length and address length are independent.

Processor k­bit
 Memory
address bus
MAR
n­bit
data bus Up to 2 k  addressable
MDR locations

Word length = n  bits

Control lines
R /W
(          , MFC, etc.)

Connection of the memory to the processor.

COA by Athar Mohsin

 Types of Memory Unit
• Random-Access Memory (RAM)
– Static RAM (SRAM)
• Memories that consist of circuits capable of retaining their state as long
as power is applied.
• SRAMs are fast (a few nanoseconds access time) but their cost is high.
– Dynamic RAM (DRAM)
• These memory units are capable of storing information for only tens of
milliseconds, thus require periodical refresh to maintain the contents.

COA by Athar Mohsin

 Types of Memory Unit

• Read-Only Memory (ROM)

– Nonvolatile memory
– Data are written into a ROM when it is manufactured.
Normal operation involves only reading of stored data.
– ROM are useful as control store component in a micro-
programmed CPU (micro-coded CPU).
– ROM is also commonly used for storing the bootstrap
loader, a program whose function is to load the boot
program from the disk into the memory when the power is
turn on.

COA by Athar Mohsin

 Types of Memory Unit
– PROM (Programmable ROM)
• data is allowed to be loaded by user but this process is irreversible
• provide a faster and less expensive approach when only a small
number of data are required
– EPROM (Erasable, reProgrammable ROM)
• stored data can be erased by exposing the chip to ultraviolet light
and new data to be loaded
– EEPROM
• stored data can be erased electrically and selectively
• different voltages are needed for erasing, writing, and reading the
stored data

COA by Athar Mohsin

 Types of Memory Unit
– Flash memory
• similar to EEPROM technology
• it is possible to read the contents of a single cell, but it is only
possible to write an entire block of cells
• greater density, higher capacity, lower cost per bit, low power
consumption
• typical applications: hand-held computers, digital cameras, MP3
music players
• large memory modules implementation: flash cards and flash
drives

COA by Athar Mohsin

 Memory Interleaving

• There are two memory address layouts :

(a) Consecutive words in a module
– The address consists of :
• (1) high-order k bits identify a single module (0 to n-1)
• (2) low-order m bits point to a particular word in that module
• (3) Accessing consecutive addresses will keep module
busy.

COA by Athar Mohsin

 Memory Interleaving

• Main memory is structured as a number of physical modules (chip).

• Each memory module has its own Address Buffer Register (ABR) and
Data Buffer Register (DBR).
• Memory access may proceed in more than one module simultaneously →
the aggregate rate of transmission of words to and from the main memory
can be increased.
• How individual addresses are distributed over the modules is critical in
determining the average number of modules that can be kept busy.

COA by Athar Mohsin

 Memory Interleaving

k  bits m  bits
Module Address in module MM address

ABR DBR ABR DBR ABR DBR

Module Module Module

0 i n ­1

(a) Consecutive words in a module

COA by Athar Mohsin

 Memory Interleaving

(b) Consecutive words in consecutive modules

– The address consists of :
• (1) low-order k bits determine a module
• (2) high-order m bits name a location within that module
• (3) Accessing consecutive addresses will keep modules busy at
any one time
– It is called Memory Interleaving.
– Faster access to a block of data.
– Higher average utilization of the memory system.

COA by Athar Mohsin

 Memory Interleaving

m bits k bits
Address in module Module MM address

ABR DBR ABR DBR ABR DBR

Module Module Module

k
0 i 2 ­ 1

(b) Consecutive words in consecutive modules

COA by Athar Mohsin

 The memory
• A single shared memory module causes
sequentialization of access.
• Memory interleaving,
– splits memory across multiple memory modules (or
banks), can be used to help relieve this.
• With low-order interleaving,
– the low-order bits of the address are used to select the
bank;
• high-order interleaving,
– the high-order bits of the address are used.

COA by Athar Mohsin

 Memory interleaving
• High-order interleaving, distributes the addresses so that
each module contains consecutive addresses, as we see
with the 32 addresses

• Low-order interleaved memory places consecutive words

of memory in different memory modules.

COA by Athar Mohsin

 Memory interleaving
• Interleaving is an advanced technique used by high-
end motherboards/chipsets to improve memory
performance.
• Memory interleaving increases bandwidth by
allowing simultaneous access to more than one
chunk of memory.
• This improves performance because the processor
can transfer more information to/from memory in the
same amount of time, and helps alleviate the
processor-memory bottleneck that is a major limiting
factor in overall performance.

COA by Athar Mohsin

 Interleaving
• Interleaving works by dividing the system memory into
multiple blocks.
– The most common numbers are two or four, called two-way or four-
way interleaving, respectively.
– Each block of memory is accessed using different sets of control lines,
which are merged together on the memory bus.
• When a read or write is begun to one block, a read or write to other blocks
can be overlapped with the first one.
• The more blocks, the more that overlapping can be done.
– As an analogy, consider eating a plate of food with a fork.
• Two-way interleaving would mean dividing the food onto two plates and
eating with both hands, using two forks.
• Four-way interleaving would require two more hands.
– Remember that here the processor is doing the "eating" and it is much faster
than the forks (memory) "feeding" it (unlike a person, whose hands are
generally faster.)

COA by Athar Mohsin

 Interleaving
• As an example of interleaving consider the following
case of a processor with a 33 MHz system bus
accessing 70 ns memory:
– Each clock cycle takes about 30 ns.
• If the processor wants to write to a block of RAM, it will have to
insert 2 wait states between consecutive writes, meaning that for
this example it will take 90 ns for each write.
– However, if each of 2 banks of RAM can be accessed
separately,
• then instead of inserting 2 wait states and leaving the processor
idle, it will instead access the second bank of memory during the
next clock cycle and insert only one wait state.
– This has effectively doubled memory throughput.

COA by Athar Mohsin

 Interleaving
• To get the best performance from this type of memory system,
– consecutive memory addresses are spread over the different blocks of
memory.
• if you have 4 blocks of interleaved memory, the system doesn't fill the first
block, and then the second and so on.
• It uses all 4 blocks, spreading the memory around so that the interleaving
can be exploited.
• Interleaving is an advanced technique that is not generally
supported by most PC motherboards, most likely due to cost.
– It is most helpful on high-end systems, especially servers, that have to
process a great deal of information quickly.
– The Intel Orion chipset is one that does support memory interleaving.

COA by Athar Mohsin

 Quiz # 2
Time 15 mis
Marks 10

COA by Athar Mohsin

 Quiz # 2
• How many bits would you need to address a 2M × 32
memory if
– a. The memory is byte-addressable?
– b. The memory is word-addressable?
• Suppose that a 2M x 16 main memory is built using
256K × 8 RAM chips and memory is word-
addressable.
– a. How many RAM chips are necessary?
– b. How many RAM chips are there per memory word?
– c. How many address bits are needed for each RAM chip?
– d. How many banks will this memory have?
– e. How many address bits are needed for all of memory?

COA by Athar Mohsin

 Solution
• How many bits would you need to address a 2M × 32 memory if
– a. The memory is byte-addressable?
– b. The memory is word-addressable?
– Ans.
• a. There are 2M × 4 bytes which equals 2 × 220 × 22 = 223 total bytes, so 23 bits are
needed for an address
• b. There are 2M words which equals 2 × 220 = 221, so 21 bits are required for an
address
• Suppose that a 2M x 16 main memory is built using 256K × 8 RAM chips
and memory is word-addressable.
– a. How many RAM chips are necessary?
• 16 (8 rows of 2 columns)
– b. How many RAM chips are there per memory word?
• 2
– c. How many address bits are needed for each RAM chip?
• 256 k = 218 so 18 bits
– d. How many banks will this memory have?
• 8
– e. How many address bits are needed for all of memory?
• 2M = 221 so 21 bits
COA by Athar Mohsin