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EE5900 Advanced Embedded System For Smart Infrastructure

RMS and EDF Scheduling

Priority-driven Preemptive Scheduling


Assumptions & Definitions Tasks are periodic No aperiodic or sporadic tasks Job (instance) deadline = end of period No resource constraints Tasks are preemptable
C Laxity (Slack) of a Task t Ti = di (t + ci) where di: deadline; t : current time; ci : remaining computation time.
i

di
Laxity

Rate Monotonic Scheduling (RMS)


Schedulability check (off-line) - A set of n tasks is schedulable on a uniprocessor by the RMS algorithm if the processor utilization (utilization test)

ci is the execution time and pi is the period, The term n(21/n -1) approaches ln 2, (0.69 as n ). - This condition is sufficient, but not necessary.
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RMS (cont.) Schedule construction (online)


- Task with the smallest period is assigned the highest priority (static priority). - At any time, the highest priority task is executed.

RMS Scheduler - Example 1


Task set: Ti = (ci, pi) [computation time, period] T1 = (2,4) and T2 = (1,8)

Schedulability check:
2/4 + 1/8 = 0.5 + 0.125 = 0.625 2(2 -1) = 0. 82
Active Tasks : {T1, T2}
Active Tasks : {T2} Active Tasks : {T1}

T11 0 2

T21 3 4

T12 6 8

RMS scheduler Example 2


Task set: Ti = (ci, pi) T1 = (2,4) and T2 = (4,8)

Schedulability check:
2/4 + 4/8 = 0.5 + 0.5 = 1.0 > 2(2 -1) = 0. 82
Active Tasks : {T1, T2}
Active Tasks : {T2} Active Tasks : {T2, T1} Active Tasks : {T2}

T11 0 2

T21 3 4

T12 6

T21 8

Some task sets that FAIL the utilization-based schedulability test are also schedulable under RMS

RMS is not optimal


T1=(1,2) and T2=(2.5,5)

Earliest Deadline First (EDF)


Schedulability check (off-line) - A set of n tasks is schedulable on a uniprocessor by the EDF algorithm if the processor utilization.

This condition is both necessary and sufficient. - Least Laxity First (LLF) algorithm has the same schedulability check.
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EDF/LLF (cont.)
Schedule construction (online) EDF/LLF: Task with the smallest deadline/laxity is assigned the highest priority (dynamic priority). At any time, the highest priority task is executed. It is optimal (i.e., whenever there is a feasible schedule, EDF can always compute it) when preemption is allowed and no resource constraint is considered. Given any two tasks in a feasible schedule, if they are not scheduled in the order of earliest deadline, you can always swap them and still generate a feasible schedule.

EDF scheduler - Example


Task set: Ti = (ci, pi, di) T1 = (1,3,3) and T2 = (4,6,6) Schedulability check: 1/3 + 4/6 = 0.33 + 0.67 = 1.0 Active Tasks : {T2} Active Tasks : {T2, T1} Active Tasks : {T1}

Active Tasks : {T1, T2}

T11 0 1

T21 3

T21 5

T12 6

Unlike RMS, Only those task sets which pass the schedulability test are schedulable under EDF

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Comparison of RMS and EDF


EDF schedule
T1
0 5 10 15 20 25 30 35

Process Period, T T1 5 T2 7

WCET, C 2 4

T2
0 7 14 21 28 35

RMS schedule
T1 0 T2 0 7 14 21 28 35 5 10 15 20 25 30

Deadline miss

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Resource sharing Periodic tasks Task can have resource access Semaphore is used for mutual exclusion RMS scheduling

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Background Task State diagram Ready State: waiting in ready queue Running State: CPU executing the task Blocked: waiting in the semaphore queue until the shared resource is free Semaphore types mutex (binary semaphore), counting semaphore

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Task State Diagram


scheduling Activate READY RUN Termination

Preemption Signal free resource WAITING Wait on busy resource

Process/Task state diagram with resource constraints

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Priority Inversion Problem


Priority inversion is an undesirable situation in which a higher priority task gets blocked (waits for CPU) for more time than that it is supposed to, by lower priority tasks. Example: Let T1 , T2 , and T3 be the three periodic tasks with decreasing order of priorities. Let T1 and T3 share a resource S.
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Priority Inversion - Example


T3 obtains a lock on the semaphore S and enters its critical section to use a shared resource.

T1 becomes ready to run and preempts T3. Then, T1 tries to enter its critical section by first trying to lock S. But, S is already locked by T3 and hence T1 is blocked. T2 becomes ready to run. Since only T2 and T3 are ready to run, T2 preempts T3 while T3 is in its critical section. Ideally, one would prefer that the highest priority task (T1) be blocked no longer than the time for T3 to complete its critical section. However, the duration of blocking is, in fact, unpredictable because task T2 got executed in between.
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Makes a Priority Inversion example

T1 Highest priority

T1

Resource S is A higher available and T1 priority task request for is scheduled resource S and waits for a gets blocked lower priority here task T1

T2 completes
Preempted by higher priority task T1 K2 T3 L1 T2 T3 completes Preempted by higher K3 priority task T2 T3

T3 is the Medium only priority active task T3 Least priority T1 and T3 share resource S

T2

K1 T3

Total blocking time for task T1 = (K2+K3) + (L1)

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Priority Inheritance Protocol


Priority inheritance protocol solves the problem of priority inversion.

Under this protocol, if a higher priority task TH is blocked by a lower priority task TL, because TL is currently executing critical section needed by TH, TL temporarily inherits the priority of TH.
When blocking ceases (i.e., TL exits the critical section), TL resumes its original priority. Unfortunately, priority inheritance may lead to deadlock.
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Resource access control - example


Task Ti ci pi c ix c iy c iz

T1 T2 T3

2 4 2

8 12 6

2 0 1

0 4 1

0 0 0

T2 and T3 have access to a shared resource R cix : Task duration before entering the critical section ciy : Critical section duration ciz : Task duration after the critical section ci = cix + ciy + ciz By RMS, T3 > T1 > T2

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Schedules
RMS Schedule Locks R Direct blocking of T3 by T2 Preempted by T3 Release R T1 2 pi 8 c ix 2 c iy 0 4 c iz 0 T2 6 T3 T2 7 8 T1 10 T2 T3 T3 14 T2 16

T3 0 Task Ti T1 ci 2

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Priority inversion of T3 by T1

T2
T3

4
2

12
6

0
1

4
1

0
0

RMS Schedule with Priority Inheritance Protocol Direct blocking of T3 by T2

T3
0

T1

T2

T3

T2

T3

T1

T3

T2

Inheritance blocking of T1 by T2

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Priority Inheritance Protocol Deadlock


Assume T2 has higher priority than T1

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Priority Ceiling Protocol


Priority ceiling protocol solves the priority inversion problem without getting into deadlock. For each semaphore, a priority ceiling is defined, whose value is the highest priority of all the tasks that may lock it. When a task Ti attempts to execute one of its critical sections, it will be suspended unless its priority is higher than the priority ceiling of all semaphores currently locked by tasks other than Ti. If task Ti is unable to enter its critical section for this reason, the task that holds the lock on the semaphore with the highest priority ceiling is said to be blocking Ti and hence inherits the priority of Ti.

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Priority Ceiling Protocol - properties


This protocol is the same as the priority inheritance protocol, except that a task Ti can also be blocked from entering a critical section if any other task is currently holding a semaphore whose priority ceiling is greater than or equal to the priority of task Ti.

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Priority Celiling Protocol - Example


For the previous example, the priority ceiling for both CS1 and CS2 is the priority of T2.

From time t0 to t2, the operations are the same as before.


At time t3, T2 attempts to lock CS1, but is blocked since CS2 (which has been locked by T1) has a priority ceiling equal to the priority of T2.

Thus T1 inherits the priority of T2 and proceeds to completion, thereby preventing deadlock situation.
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Scheduling tasks with precedence relations


Conventional task set {T1, T2} Scheduler

T1

T2

task set with precedence constraints

Modify task parameters in order to respect precedence constraints

Scheduler

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Modifying the task parameters for RMS While using the RMS scheduler the task parameters (ready time) need to be modified in order to respect the precedence constraints
Ti Tj

Rj* Max (Rj, Ri*) where Ri* is the modified ready time of the task Ti Priority Prioi Prioj
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Modifying ready times for RMS: example

T1 1

T2 2 Initial Task Parameters

T3 2

T4 1

Task T1 T2 T3

Ri 0 5 0 0 0

Ci 1 2 2 1 3

Di 5 7 5 10 12

T5 3

T4 T5

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Modifying the Ready times for RMS


R1 = 0 T1 1 R3 = max(R1, R3) R3 = 0 R3 = 0 T3 2 T2 2 R2 = 5 R4 = max(R1, R2,R4) Initial Task Parameters T4 1 R4 = 0 R4 = 5

Task T1 T2 T3

Ri 0 5 0 0 0

Ci 1 2 2 1 3

Di 5 7 5 10 12

T5 3

R5 = 0 R5 = 5

T4 T5

R5 = max(R3, R4,R5)

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Modified Ready times for RMS


R1 = 0 T1 1 T2 2 Modified Task Parameters T3 2 R3 = 0 T4 1 R4 = 5 R2 = 5

Task T1 T2 T3

Ri 0 5 0 5 5

Ci 1 2 2 1 3

Di 5 7 5 10 12

T5 3

R5 = 5

T4 T5

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Assigning task priorities for RMS


R1 = 0 T1 1 T2 2 R2 = 5

T3 2

R3 = 0

Assume all tasks of a connected component have the same period. Therefore, as per RMS all tasks will have a tie. We assign priorities to break the ties.
Modified Task Parameters

T4 1

R4 = 5

Task

Ri

Ci

Di

Priority

T1
T5 3

0 5 0 5
5

1 2 2 1
3

5 7 5 10
12

3 4 2 1
0
30

T2
R5 = 5

T3 T4
T5

Modifying task parameters for EDF While using the EDF scheduler the task parameters need to be modified in order to respect the precedence constraints
Ti Tj

Rj* Max (Rj, (Ri* + Ci)) Di* Min (Di, (Dj* Cj))

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Modifying the Ready times for EDF


R1 = 0 T1 1 R3 = max(R1 + C1, R3) R3 = 0 R3 = 1 T2 2 R2 = 5

R4 = max(R1+C1, R2+C2,R4)
Initial Task Parameters

T3 2

T4 1

R4 = 0 R4 = 7

Task T1 T2 T3

Ri 0 5 0 0 0

Ci 1 2 2 1 3

Di 5 7 5 10 12

T5 3

R5 = 0 R5 = 8

T4 T5

R5 = max(R3+C3, R4+C4,R5)

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Modifying the Ready times for EDF


R1 = 0 T1 1 T2 2 Modified Task Parameters T3 2 R3 = 1 T4 1 R4 = 7 R2 = 5

Task T1 T2 T3

Ri 0 5 1 7 8

Ci 1 2 2 1 3

Di 5 7 5 10 12

T5 3

R5 = 8

T4 T5

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Modifying the Deadlines for EDF


D2 = Min( (D4 C4), (D3 C3), D1) D1 = 5 D1 = 3 T1 1 D2 = 7 D2 = 7

T2 2

D2 = Min( (D4 C4), D2)

Modified Task Parameters T3 2 D3 = 5 D3 = 5 T4 1 D4 = 10 D4 = 9

Task T1 T2 T3

Ri 0 5 1 7 8

Ci 1 2 2 1 3

Di 5 7 5 10 12

T5 3

D5 = 12

T4 T5

D3 = Min( (D5 C5), D3) D4 = Min( (D5 C5), D4)

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Modifying the Deadlines for EDF


D1 = 3 T1 1 D2 = 7

T2 2

Modified Task Parameters T3 2 D3 = 5 T4 1

Task
D4 = 9

Ri 0 5 1 7 8

Ci 1 2 2 1 3

Di 3 7 5 9 12

T1 T2 T3

T5 3

D5 = 12

T4 T5

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