8x8 SRAM

Wing Chan Mahavir Sheth Junghoon Kang Shalin Shah

Advisor: Dave Parent 12/6/04

Agenda
Abstract Introduction
Simple Theory Back Ground information

Summary of Results Project Details Results Cost Analysis Conclusions

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Abstract
We designed an 8x8 SRAM that operates at 200Mhz and uses 15.2mW of power and occupies an area of

Introduction
The SRAM project helped us understand the IC design process bit (schematic and layout) keeping in word mind the delay, power, and area 3 specifications. SRAM is a 6-transistor bistable 1 latch that stores one of the two possible states as long as power supply is provided. W Equations used: W L 3 0.34 L 5 0.7 W W L 3 L 1
bit_b
5 6 4
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Project Details
The SRAM Circuit is a 8 bit 64 cell in a standard 8 column by 8 row design. Each Row of the cell is selected by the 3 x 8 decoder. The Data is read in at the positive edge of the clock from the DFF and feed into the 8 input lines. Each Row has two write circuits that writes to the bit lines and inverted bit lines that provides the voltages for the sense amplifier for reading when read enable is selected.
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Calculated:

PHL

5ns 0.42ns 12

Observed:

Area = 273cm x 495cm

=0.135

cm

Total delay: 3.7ns

Power = 6.08mA * 2.5V = 15.2mW Or 0.11W/

cm

Longest Path Calculations

Logic Level Gate Cg to Drive #C #CD #LNs D P N s s #LP s WN (H.C) WP (H.C) WN (S) WP (S) WN (L) WP (L) Cg to Gate 1 2 3 4 5 Decoder Inv Nand3 InvBuffer DFF 20.3fF 16fF 80fF 30fF 1 5 1 1 3 1 1 3 1 1 1 1 5.55 4.95 4.55 3.3 4.8 2.55 6.3 5.3 5 2.62 2.69 4.35 5.5 3.35 4.54 2.33 7.05 6 5.4 2.62 2.69 4.95 6 4.05 4.54 2.33 18.3fF

20.3fF
16fF 8.2fF

Schematic

Schematic

Schematic

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Layout

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Verification

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Simulations

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Cost Analysis
Spend over 50 hrs verifying circuit logic and timing. Over 100 hrs doing layout and post extract simulation.

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Lessons Learned
Post extract simulation does not always matches the schematic circuit even when LVS matches-specially if there are analog circuit components.

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Summary
The SRAM project covers many areas thats important to learning IC design-from timing verification to layout.
RESULT: - schematic simulation showed correct logic for the SRAM - meets timing specification of 5ns - meets power specification of 23mW(15.2mW) - LVS matches the layout with schematic successfully

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Post extracted simulation does not charge and discharge to correct logic.
POSSIBLE REASONS: - larger than expected capacitance on the bit lines to charge up - needs pre-charge bit lines before each read cycle.

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Acknowledgements
Thanks to Synopsys for Software donation Professor Parent

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