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Mani Srivastava UCLA - EE Department Room: 6731-H Boelter Hall Email: mbs@ee.ucla.edu Tel: 310-267-2098 WWW: http://www.ee.ucla.edu/~mbs
Fabrication
Manufacturing test Chips to customer
Definitions
Design synthesis: Given an I/O function, develop a procedure to manufacture a device using known materials and processes. Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function. Test: A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect.
make testing of manufactured part swift & comprehensive provide controllability and observability
DFT mantra
provide circuitry to enable test provide test patterns that guarantee reasonable coverage
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
Test Classification
Diagnostic test
used in chip/board debugging defect localization used to determine whether a chip is functional simpler than diagnostic test; must be simple & swift x e [v,i] versus x e [0,1] check parameters such as NM, Vt, tp, T
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
Verifies correctness of design. Performed by simulation, hardware emulation, or formal methods. Performed once prior to manufacturing. Responsible for quality of design.
Verifies correctness of manufactured hardware. Two-part process: 1. Test generation: software process executed once during design 2. Test application: electrical tests applied to hardware Test application performed on every manufactured device. Responsible for quality of devices.
High speed testers are astronomically costly! Reducing test time can help increase throughput of tester
Costs of Testing
Manufacturing test
Automatic test equipment (ATE) capital cost Test center operational cost
PI Test input
Int. bus
Logic block B
PO
Test output
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= $1.2M + 1,024 x $3,000 = $4.272M = Depreciation + Maintenance + Operation = $0.854M + $0.085M + $0.5M = $1.439M/year = $1.439M/(365 x 24 x 3,600) = 4.5 cents/second
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Roles of Testing
Detection: Determination whether or not the device under test (DUT) has some fault. Diagnosis: Identification of a specific fault that is present on DUT. Device characterization: Determination and correction of errors in design and/or test procedure. Failure mode analysis (FMA): Determination of manufacturing process errors that may have caused defects on the DUT.
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2N patterns
2N+M patterns
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Testing Approach
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Ideal tests detect all defects produced in the manufacturing process. Ideal tests pass all functionally good devices. Very large numbers and varieties of possible defects need to be tested. Difficult to generate tests for some real defects. Defectoriented testing is an open problem.
Based on analyzable fault models, which may not map on real defects. Incomplete coverage of modeled faults due to high complexity. Some good chips are rejected. The fraction (or percentage) of such chips is called the yield loss. Some bad chips pass tests. The fraction (or percentage) of bad chips among all passing chips is called the defect level.
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Transmission medium
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Testing Principle
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Combinational circuits
controllable and observable relatively easy to determine test patterns turn into combination circuits or, use self-test use self-test
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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Test Approaches
Three approaches
Ad-hoc testing Scan-based testing Self-test increasing complexity and heterogeneous combination of modules in systems-on-a-chip advanced packaging and assembly techniques extend problem to the board level
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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for given fault, determine excitation vector (called test vector) that will propagate error to primary (observable) output majority of available tools: combinational n/w only sequential ATPG available from academic research
determines test coverage of proposed test-vector set simulates correct network in parallel with faulty networks
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
Fault simulation
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Fault Modeling
Why model faults? Some real defects in VLSI and PCB Common fault models Stuck-at faults
Single stuck-at faults Fault equivalence Fault dominance and checkpoint theorem Classes of stuck-at faults and multiple faults
Transistor faults
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I/O function tests inadequate for manufacturing (functionality versus component and interconnect testing) Real defects (often mechanical) too numerous and often not analyzable A fault model identifies targets for testing A fault model makes analysis possible Effectiveness measurable by experiments
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Processing defects Missing contact windows Parasitic transistors Oxide breakdown . . . Material defects Bulk defects (cracks, crystal imperfections) surface impurities (ion migration) . . . Time-dependent failures Dielectric breakdown Electromigration . . . Packaging failures Contact degradation Seal leaks . . .
Ref.: M. J. Howes and D. V. Morgan, Reliability and Degradation Semiconductor Devices and Circuits, Wiley, 1981.
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
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Single stuck-at faults Transistor open and short faults Memory faults PLA faults (stuck-at, cross-point, bridging) Functional faults (processors) Delay faults (transition, path) Analog faults
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Fault Models
Most Popular - Stuck - at model
0 1
sa0 (output)
sa1 (input)
Covers almost all (other) occurring faults, such as opens and shorts.
Z
x1
x3
x2
[Adapted from http://infopad.eecs.berkeley.edu/~icdes ign/. Copyright 1996 UCB]
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Only one line is faulty The faulty line is permanently set to 0 or 1 The fault can be at an input or output of a gate
Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults Faulty circuit value
c
1 0
a b
d
e f
s-a-0
0(1) 1(0) 1
g
1
h i k
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Fault Equivalence
Number of fault sites in a Boolean gate circuit = #PI + #gates + #(fanout branches). Fault equivalence: Two faults f1 and f2 are equivalent if all tests that detect f1 also detect f2. If faults f1 and f2 are equivalent then the corresponding faulty functions are identical. Fault collapsing: All single faults of a logic circuits can be divided into disjoint equivalence subsets, where all faults in a subset are mutually equivalent. A collapsed fault set contains one fault from each equivalence subset.
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Equivalence Rules
sa0 sa0 sa1
sa0 sa1
sa1
sa0 sa1
AND
sa0 sa1
OR
sa0 sa1
WIRE
NOT
sa1 sa0
NAND
sa0 sa1
NOR
FANOUT
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
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Equivalence Example
sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 20 Collapse ratio = ----- = 0.625 32 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 Faults in red removed by equivalence collapsing
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
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Fault Dominance
If all tests of some fault F1 detect another fault F2, then F2 is said to dominate F1. Dominance fault collapsing: If fault F2 dominates F1, then F2 is removed from the fault list. When dominance fault collapsing is used, it is sufficient to consider only the input faults of Boolean gates. See the next example. In a tree circuit (without fanouts) PI faults form a dominance collapsed fault set. If two faults dominate each other then they are equivalent.
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Dominance Example
All tests of F2 F1 s-a-1 F2 s-a-1 001 110 101 010 011
000
100
s-a-1 s-a-1
Only test of F1
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Checkpoints
Primary inputs and fanout branches of a combinational circuit are called checkpoints. Checkpoint theorem: A test set that detects all single (multiple) stuck-at faults on all checkpoints of a combinational circuit, also detects all single (multiple) stuck-at faults in that circuit.
Total fault sites = 16 Checkpoints ( ) = 10
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Potentially-detectable fault -- Test produces an unknown (X) state at PO; detection is probabilistic, usually with 50% probability. Initialization fault -- Fault prevents initialization of the faulty circuit; can be detected as a potentially-detectable fault. Hyperactive fault -- Fault induces much internal signal activity without reaching PO. Redundant fault -- No test exists for the fault. Untestable fault -- Test generator is unable to find a test.
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A multiple stuck-at fault means that any set of lines is stuck-at some combination of (0,1) values. The total number of single and multiple stuck-at faults in a circuit with k single fault sites is 3k-1. A single fault test can fail to detect the target fault if another fault is also present, however, such masking of one fault by another is rare. Statistically, single fault tests cover a very large number of multiple faults.
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MOS transistor is considered an ideal switch and two types of faults are modeled:
Stuck-open -- a single transistor is permanently stuck in the open state. Stuck-short -- a single transistor is permanently shorted irrespective of its gate voltage.
Detection of a stuck-open fault requires two vectors. Detection of a stuck-short fault requires the measurement of quiescent current (IDDQ).
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Sequential effect
Needs two vectors to ensure detection! Other options: use stuck-open or stuck-short models This requires fault-simulation and analysis at the switch or transistor level - Very expensive!
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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Vector 1: test for A s-a-0 (Initialization vector) Vector 2 (test for A s-a-1)
VDD
0
0
A B
Stuckopen
nMOS FETs
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
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Causes short circuit between Vdd and GND for A=C=0, B=1 Possible approach: Supply Current Measurement (IDDQ) but: not applicable for gigascale integration
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VDD
Stuckshort
A B
nMOS FETs
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
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Fault models are analyzable approximations of defects and are essential for a test methodology. For digital logic single stuck-at fault model offers best advantage of tools and experience. Many other faults (bridging, stuck-open and multiple stuck-at) are largely covered by stuck-at fault tests. Stuck-short and delay faults and technology-dependent faults require special tests. Memory and analog circuits need other specialized fault models and tests.
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Determine a minimum set of excitation vectors that cover a significant portion of the fault set as defined by the adopted fault model An approach: start form random set of patterns
use fault simulation to determine how many potential faults are detected iteratively add or remove extra vectors determines fault coverage correct circuit simulated in parallel with a number of faulty ones, each with a single fault
results compared
Fault simulation
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For n-input circuit, generate all 2n input patterns Infeasible, unless circuit is partitioned into cones of logic, with 15 inputs
Perform exhaustive ATPG for each cone Misses faults that require specific activation patterns for multiple cones to be tested
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Random-Pattern Generation
Flow chart for method Use to get tests for 60-80% of faults, then switch to Dalgorithm or other ATPG for rest
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Fault Simulation
A circuit A sequence of test vectors A fault model Fault coverage - fraction (or percentage) of modeled faults detected by test vectors Set of undetected faults Determine test quality and in turn product quality Find undetected fault targets to improve tests
Determine
Motivation
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Low
Test generator
Add vectors
Adequate Stop
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
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Serial Algorithm
Algorithm: Simulate fault-free circuit and save responses. Repeat following steps for each fault in the fault list:
Modify netlist by injecting one fault Simulate modified netlist, vector by vector, comparing responses with saved responses If response differs, report fault detection and suspend simulation of remaining vectors
Advantages:
Easy to implement; needs only a true-value simulator, less memory Most faults, including analog faults, can be simulated
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Disadvantage: Much repeated computation; CPU time prohibitive for VLSI circuits Alternative: Simulate many faults together
Fault-free circuit
Circuit with fault f1 Comparator Circuit with fault f2 f2 detected? Comparator f1 detected?
Test vectors
fn detected?
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Best with two-states (0,1) Exploits inherent bit-parallelism of logic operations on computer words Storage: one word per line for two-state simulation Multi-pass simulation: Each pass simulates w-1 new faults, where w is the machine word length Speed up over serial method ~ w-1 Not suitable for circuits with timing-critical and nonBoolean logic
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a
b
1 1 1 1 0 1
1 0 1
c s-a-0 detected
e
0 0 0
s-a-0
1 0 1
s-a-1
0 0 1
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Event-driven simulation of fault-free circuit and only those parts of the faulty circuit that differ in signal states from the fault-free circuit. A list per gate containing copies of the gate from all faulty circuits in which this gate differs. List element contains fault ID, gate input and output values and internal states, if any. All events of fault-free and all faulty circuits are implicitly simulated. Faults can be simulated in any modeling style or detail supported in true-value simulation (offers most flexibility.) Faster than other methods, but uses most memory.
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a0
0
1 0
b0
0
c0
0
1 1
e0
0
a b
1 1 1 1 1
c d
e
0
1 0
g
0 1
1 0
0 0
a0
0
b0
0 0 1 1
c0
0
0 0 1 1
e0
0
b0
d0
f1
g0
f1
d0
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Fault Sampling
A randomly selected subset (sample) of faults is simulated. Measured coverage in the sample is used to estimate fault coverage in the entire circuit. Advantage: Saving in computing resources (CPU time and memory.) Disadvantage: Limited data on undetected faults.
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Carry Circuit
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Functional ATPG generate complete set of tests for circuit inputoutput combinations 129 inputs, 65 outputs: 2129 = 680,564,733,841,876,926,926,749, 214,863,536,422,912 patterns Using 1 GHz ATE, would take 2.15 x 1022 years Structural test: No redundant adder hardware, 64 bit slices Each with 27 faults (using fault equivalence) At most 64 x 27 = 1728 faults (tests) Takes 0.000001728 s on 1 GHz ATE Designer gives small set of functional tests augment with structural tests to boost coverage to 98+ %
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Fault enabling
1 1 Fault propagation 0
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Represent two machines, which are simulated simultaneously: Good circuit machine (1st value) Bad circuit machine (2nd value)
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1
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
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67
0
D D D
1 1
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69
70
71
72
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Ad-hoc Test
Memory
address data data
Memory
address
test
select
Processor Processor
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Design-for-Testability
Extra hardware
no functionality other than to improve testability take penalty in area and performance if observability and controllability improved e.g. Test port multiplex test andn ormal signals on same pins
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Scan-based Test
ScanIn ScanOut Out
Register
Logic A
Register
In
Combinational
Combinational Logic B
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Out0
Out1
Out2
Out3
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Level sensitive Scan Design (LSSD) Introduced at IBM and set as company policy
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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Scan-Path Register
OUT SCAN SCANIN PHI2 PHI1 SCANOUT
IN
LOAD
KEEP
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Scan-Path Testing
A REG[1] B REG[0] SCANIN REG[2] REG[3]
REG[5]
SCANOUT
OUT
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Scan-in Scan-out
si
so scan path
Bonding Pad
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Test Controller
Rapidly becoming more important with increasing chip-complexity and larger modules
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
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Signature Analysis
In Counter R
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BILBO
B0 B1 ScanIn ScanOut R S0 R S1 R S2
mux
D0
D1
D2
B0 B1 1 0 1 0 1 0 0 1
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BILBO Application
ScanIn ScanOut
BILBO-A
Logic
BILBO-B
In
Combinational
Combinational Logic
Out
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Memory Self-test
data -in Memory FSM Under Test address & R/W control Analysis data-out Signature