Baldev Ram Mirdha Institute Of Technology, Jaipur

Smart Dust Core Architecture

Submitted To: Mr. Mukesh Jakhar Submitted By: Baldev Ram M10EC024

Contents
What is Smart Dust? What is Smart Dust Core Architecture ? Architecture Of S.D.C.A. Application Of S.D.C.A. Conclusion.

SMART DUST ?

Smart Dust is a system consisting of various tiny micro-electro-mechanical systems (MEMS) that have the ability to detect certain phenomena (typically light, temperature , vibration, chemicals) . They are networked wirelessly, so they can be scattered over a certain

Smart Dust Core Arch. Overview

Autonomous sensing and communications in 1 mm3 Multiple sensors: temperature, light, vibration, etc. Batteries: 1 J/mm3 Downlink: broadcast only Uplink: CCR draws 6.4 pJ/bit

System Diagram
Sensors
ADC

Core
Transceiver back end

Power Supply

Receiver Front End

Real Time Clock

Sensor Signal Processing

Computation Memory CCR Driver

Design Goals

Minimize energy through architecture Dynamic re-configurability

Minimum energy ASIC implementation How much is necessary tradeoff with ASIC mapping Energy driven operation modes Typical application scenario to guide design Detect heat and vibration of vehicles Real time sensor readings Logged sensor readings

Military base monitoring

Desired Operations

Immediate

Transmit ID Mote health report Transmit current readings from one/all sensors Send logged data for sensor X Calibrate real-time clock Start logging data from sensor X sampled every T seconds Set logging threshold and filter coefficients Set ScatterCast interval to T seconds Set your wakeup interval to T seconds

Reconfiguration

One Approach: Golden Processor

Golden Processor: Features

Laser Reprogrammable Gated clocks everywhere Processor stall mode Eight execution phases

1 CPI including fetch No pipelining to reduce overhead Forced sequencing

Minimize glitching Prevent bus conflicts and thus short circuit current

Robust to delay variations from process spreads, voltage swings (will test from 0.3V to 1.4V), and temperature

Golden Processor: Features

Laser Reprogrammable Gated clocks everywhere Processor stall mode Eight execution phases

1 cpi including fetch No pipelining to reduce overhead Forced sequencing Robust to delay variations from process spreads, voltage swings (will test from 0.3V to 1.4V), and temperature
Minimize glitching Prevent bus conflicts and thus short circuit current

New Approach: Top-Level Diagram

Setup Memroy Sensors Timer Bank ADC

Power Supply

Receiver Front End

Reconfigurable Datapath Components

CCR Driver SRAM

Real Time Clock

Conclusions
Smart Dust needs minimum energy controller New non-microprocessor architecture designed
Timer controlled Reconfigurable data path Should be much lower energy than a microprocessor architecture, but unconfirmed

Thank You

QUERY ?