Central Processing Unit

The organization of a simple computer with one CPU and two I/O devices

CPU
Brain of the computer system Controls all internal and external devices Performs arithmetic and logic operations Operates on binary data (0s and 1s) Controls usage of main memory and sequence of operations Arithmetic/Logic Unit, Control Unit and Registers Three main subsystems

Arithmetic/Logic Unit (ALU)

ALU contains the electronic circuitry that executes all arithmetic and logic operations on data available to it Data are inputs from designated registers Arithmetic unit carries out addition, subtraction, multiplication and division at high speeds Logic unit enables CPU to make logical operations based on the instructions provided Can compare letters, numbers or special characters for less than, equal to and greater than conditions

Registers
Registers are special purpose, high speed temporary memory units Temporary storage areas for holding information such as data, instructions, addresses and intermediate results of calculations CPUs working memory, a special additional storage that offers advantage of speed Work under the direction of control unit to accept, hold or transfer data or instructions Instruction addresses are stored in consecutive registers and executed sequentially Control unit reads an instruction in memory by a specific address in the register and executes it

AX - the accumulator register (divided into AH / AL). BX - the base address register (divided into BH / BL) CX - the count register (divided into CH / CL) DX - the data register (divided into DH / DL) SI - source index register DI - destination index register BP - base pointer

SP - stack pointer

Types of Registers

Program Counter Keeps track of next instruction to be executed Instruction Register Holds the instruction register to be decoded by the control unit Memory Address Register Holds the address of the next location in memory to be accessed Memory Buffer Register Stores data either coming to CPU or transferred by CPU Accumulator Stores temporary results and results produced by ALU Data Register Storing the operands and other data The length of register - Should have the same number of bits as its type eg memory address or the instruction (for memory address and instruction register)

Control Unit
Control unit of the CPU contains circuitry that uses electrical signals to carry out, execute stored program instructions Like an orchestra leader who himself does not play but directs others to play Directs other party of the system to execute instructions by communicating with ALU and memory Controls I/O devices and transfer of data to and from primary memory Instructions are retrieved from primary storage one at a time Uses the instruction register for holding the current instruction and instruction pointer for holding the next instruction Each instruction is decoded, based on the instruction control unit co-ordinates the execution of the instruction with ALU and other components Issues commands to all elements of CPU Determines what data is needed, where it is stored and where to store the results of operation Administers the movement of large amount of data and instructions used by the computer To maintain proper sequence of events, CU uses clock inputs

System Bus
Bus is a set of connections between two or more components/devices, designed to transfer several/all bits of a word from a source to destination Physically, a bus is a number of parallel electrical conductors. These circuits are normally imprinted on printed circuit boards. Bus extends across system components, which can be tapped into bus lines Bus has several lines, each line capable of transferring only one bit at a time 8 lines needed to transfer 8 bits at a time over a bus Shared bus source can transmit data at one time but one or more can receive the data A bus that connects CPU, memory and I/O is a System Bus System bus can have 80 to 100 lines

System Bus
Data lines Provides the path for moving data between system modules- Data lines are also called as data bus. Contains 8, 16 and 32 bits separate lines The number of lines in a data bus is called the width of the data bus Larger the width better the performance of the computer system Address lines Used to designate the source of data for data bus For reading or writing information on to memory CPU need to provide address The address is provided by address bus Width of the memory specifies the maximum possible memory supplied by the system Control lines Control the access to data and address bus Used for transmission of commands and timing signals between system modules Timing signals indicate whether data and address information is valid or not Command signals specify which operations to be performed

Main memory Unit

Holds data and instructions for processing Logically an integral component of CPU Physically a separate part placed on the mother board Stores program instruction or data as longs as program is in operation CPU accesses memory randomly RAM and ROM RAM Directly provides required information to the processor. Block of sequential memory locations, each of which has a unique address determining the location and the locations contain a data element. Storage locations in main memory are addressed directly by CPUs instructions Volatile in nature- information will be lost if power is switched off ROM Read only memory Stores initial start-up instruction and routines in BIOS (basic input/output system) which can only be read by CPU Contents are not lost even power is switched off Non-volatile

Cache Memory
Cache is a high speed, expensive piece of memory, used to speed up memory retrieval process Stores data that is frequently used and accessed Incorporated in the processor L1 Cache closest to processor and is the primary cache, saves time consuming access to the main memory. Ranges from 8 to 64 KB, with more memory on new processors Fast because its integrated with the processor Handles command instructions (instruction cache) and data (data cache) L2 Cache Larger but slower in speed compared to L1, usually 64KB to 2 MB in size, also incorporated in CPU, information not found in L1 can be retrieved from L2 L3 Cache Extra Cache built into motherboard between processor and main memory to speed up processing time, reduces the time gap between request and retrieve of data and instructions, quicker than main memory, can store up to 3 MB of storage

Communication amount various units Processor to Memory communication

Information transfer Processor places the address in memory address register through the address bus issues a read command through control bus Memory places retrieved data on data bus which is transferred to processor Processor places the address in memory address register through the address bus The processor transmits the data to be written through data bus The processor issues a write command to memory by the control bus Data is written in memory at address specified in memory address register

Writing to memory

Speed mismatch between memory and processor, memory access is generally slower than CPU access time, so processor is forced to wait for the data. Cache memory improves the performance by being a intermediate buffer

Communication amount various units Processor to I/O devices communication

I/O devices are connected to CPU through system bus DMA controller handles the data transfers on behalf of CPU Controls the operation of the I/O device Can use system bus when CPU does not require it or free it when CPU requires Allows peripheral devices to read or write data in main memory without going through CPU Direct Memory Access increases speed of I/O operations by taking over buses and eliminating CPU intervention

Instruction Format
An instruction consists of an opcode and one or more operands, which may be addressed implicitly or explicitly Instruction format specifies the layout of the bits allocated to the elements of an instruction Instruction length determines the flexibility of the machine. The decision on length depends on the memory size, memory org and memory transfer length Tradeoff between no. of opcodes and addressing capability. More opcodes means more bits in the opcode field and this reduces the no. of bits for addressing for a fixed length format

Instruction Format
Typically first 3 bits represent the opcode Final 6 bits represent the operands The middle bit represent whether the operand is memory address or data Three types of instructions :
Data Transfer Arithmetic instructions Program Control Input-Output

Instruction Cycle
Basic function of CPU is execution of a program Program is a set of instructions stored in memory CPU fetches instructions and executes within CPU, execution takes place in CPU registers Fetch Cycle :
Program counter MAR (address transferred to memory address register) MAR => memory => MBR (transferred through data lines by co-ordinated by CU) MBR => IR (transferred to Instruction Register) CU => IR (CU increments PC to point to next address register) In the IR, unique bi patterns that represent the machine language are extracted and sent to the decoder

Instruction Cycle
Decode Cycle : For recognizing which operation the bit pattern
The operation code of the instruction is first read and then interpreted in the machine language The data required by the instruction (operand) is then transferred to DR (data register)

Execute Cycle : Once transferred to DR, the execute cycle can begin Complex operations performed with four category of operations
CPU Memory : Data can be transferred from memory to CPU and vice versa CPU-I/O : Data transfer between I/O and CPU Data processing : Perform arithmetic or logic operation on ALU Control : An instruction to change the sequence of operations may be specified The results from the execution cycle are stored in memory buffer register Then the results from MBR are stored back in the main memory IR => MAR (transferring address portion of the instruction from IR to MAR) MAR => MBR ( CPU transfers instruction located at MAR to MBR via data lines connecting CPU to memory) MBR => ACC (data transferred to ACC)

Store Cycle :

Load ACC, memory : -

Next instruction is fetched and process starts again

Instruction Set
Collection of processors operations is an instruction set Its hard wired (embedded) in the processor Determines the machine language for the processor More complicated the instruction set, the slower the processor works Processors differ from one another by their instruction set Compatible if same programs run on different processors (eg JVM) Program written for IBM may not run on apple computers as the architectures (processors) are different Each processor has an unique instruction set, machine level programs written for one processor will not work on another processor All OS and software are constructed within the boundaries of processors instruction set Design of the instruction set becomes an important aspect of computer archetecture Two types of architecture : Complex instruction set Computer, Reduced instruction set Computer

CISC and RISC

CISC :
Processors with extensive and complex Instruction set Could incorporate hard wired circuitary for performing square root or other complex operations in a single step Writing instructions is easier Saves memory

RISC :
Uses small highly optimized instructions Small number of instructions is faster than a large single instruction Pipelining allows processor to work on different steps of instruction at the same time More instructions can be executed in a shorter period of time By overlapping fetch, decode and execute cycles of two or more instructions Uses large number of registers Processors are smaller, consume less power and run cooler than CISC processors Ideal for mobile phone, PDA and digital came applications (embedded applications) Simple design also reduces the development time compared to CISC processor

CISC processors
1 Complex Instruction Set Computer (CISC) processors has a bigger instruction set with many addressing modes.

RISC processors
1.Reduced Instruction Set Computers (RISC) processors has a smaller instruction set with few addressing modes 2. It has a hard-wired programmed-unit without acontrol memory, and seperate hardware to implement each and every instruction.

2. It has to use a seperate micro-programming unit with a control memory to implement complex instructions.

3. An easy compiler design

4. The calculations are slower and precise 5. Decoding of instruction is complex 6.The Execution time is very high.

3. A complex compiler design.

4The calculations are faster and precise 5. Decoding of instruction is 6. It takes a very less execution time. 7. Since it uses a hardwired model, its not often, to take the external memory access for calculations. 8. Pipeling is not a processors. major problem and this option speeds up the

7. It frequently needs the external memory access to make calculations.

8. Pipelining does not function correctly here because of complexity in instructions. 9. These processors often stall because of pipelining problem. 10. Code Expansion is not a problem in CISC processors. 11. Disc space is wasted. 12. Used in low end applications such us Security systems, Home automation

9. Since the instructions are not complex, stalling is mostly reduced. 10. Code expansion can be a problem in some cases in RISC processors. 11. Disc space is saved. 12. Used in High end applications such us video processing, telecommunications

Processor Speed
Faster the processor better the performace Speed of computer is determined by
Clock speed of processor (eg 700 MHz) Speed and Size of data bus

A 32 bit 800 MHz processor can process 4 bytes simultaneously, 800 million cycles per second While buying computer, a perfect match between the bus size, bus speed and the speed of clock should be considered Other factors that limit the processors speed
Transmission delays on the chip (in wires that connect components together on the chip) Heat build up on the chip