Made by: Mikul Patel Amit Kumar Anil Mor Vijay Kumar Pankaj Kakkad 12213013

12116033 12116007 12116008 12213020

What is FIFO?
First In First Out(FIFO) is a method of processing

data where the data first received is the first to be sent out after processed.
For example

 For booking a train ticket, the person

entering first gets the ticket first. Or, a person who FIRST gets IN the line, is the FIRST to come OUT Similarly in memory, FIFO controller is used to read and write the data following the FIFO principle.

Problem statement:
FIFOs are used commonly in electronic circuits for buffering and flow control which is from hardware to software. In hardware form a FIFO primarily consists of a set of read and write pointers, storage and control logic. Storage may be SRAM, flip-flops, latches or any other suitable form of storage. For FIFOs of nontrivial size a dual-port SRAM is usually used where one port is used for writing and the other is used for reading. In this project, you need to design a FIFO to store up to 1024 items of 32 bits each and a FIFO controller assuming that FIFO will not be read when it is empty, not to be written when it is full. Write and read port share a common bus.

Let us first see what are the inputs and outputs of a 32 bit input FIFO controller.

Read Write

32 bit output

Empty Full

32 bit parallel shift register

D Flip-Flop

32 bit parallel shift register

Let us see with an example, how the data will be read in and written out from the controller. For ease of understanding, consider a FIFO controller which stores maximum 5 alphabets.

WRITE

READ

Empty

Full

Up down counter

 For the proper functioning of Fifo Controller 2-bit

input and the clock reach the Register at the same time for the proper entry of the data at the proper index.
In this design we have assumed that there

is no input from the processor as any of the empty or overflow error is detected.

Components of VHDL file

Counter
VHDL Code: entity counter_4 is generic(n: natural :=2); port( clock: in std_logic; clear: in std_logic; count: in std_logic; Q: out std_logic_vector(n-1 downto 0) ); end counter_4; ----------------------------------------------------------------architecture counter_4_arch of counter_4 is signal Pre_Q: std_logic_vector(n-1 downto 0); begin -- behavior describe the counter process(clock, count, clear) begin if clear = '1' then Pre_Q<= Pre_Q - Pre_Q; elsif (clock='1' and clock'event) then if count = '1' then Pre_Q<= Pre_Q + 1; end if; end if; end process; -- concurrent assignment statement Q <= Pre_Q; end counter_4_arch; -----------------------------------------------------------------

 Decode
entity DECODER_2x4 is port( I: in std_logic_vector(1 downto 0); O: out std_logic_vector(3 downto 0) ); end DECODER_2x4; architecture DECODER_2x4_arch of DECODER_2x4 is begin O <= "0001" when I = "00" else "0010" when I = "01" else "0100" when I = "10" else "1000" when I = "11" else "XXXX";

end DECODER_2x4_arch;

 Multiplexe
entity mux_4x1 is port( I3: I2: I1: I0: S: O: in std_logic_vector(1 downto 0); in std_logic_vector(1 downto 0); in std_logic_vector(1 downto 0); in std_logic_vector(1 downto 0); in std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0)

); end mux_4x1; ------------------------------------------------architecture mux_4x1_arch of mux_4x1 is begin process(I3,I2,I1,I0,S) begin -- use case statement case S is when "00" => when "01" => when "10" => when "11" => when others => end case; end process; end mux_4x1_arch;

O <= I0; O <= I1; O <= I2; O <= I3; O <= "ZZ";

 Up-Down Counter
-------------------------------------------library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;

entity up_down_counter is port(clk, rst_a, mode_r,mode_w : in std_logic; --mode=1 up counting, mode=0 down counting q : out std_logic_vector(1 downto 0)); end up_down_counter; architecture archi of up_down_counter is signal tmp: std_logic_vector(1 downto 0); begin process (clk, rst_a) begin if (rst_a='1') then tmp <= "00"; elsif (clk'event and clk='1') then if (mode_w='1') then tmp <= tmp + 1; elsif (mode_r='1') then tmp <= tmp - 1; end if; end if; end process; q <= tmp; end archi;

 Register
library ieee ; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; --------------------------------------------------entity register_2bit is generic(n: natural :=2); port( I: clock: load: clear: Q: ); end register_2bit; architecture register_2bit_arch of register_2bit is signal Q_tmp: std_logic_vector(n-1 downto 0); begin process(I, clock, load, clear) begin in std_logic_vector(n-1 downto 0); in std_logic; in std_logic; in std_logic; out std_logic_vector(n-1 downto 0) if clear = '0' then -- use 'range in signal assigment Q_tmp <= (Q_tmp'range => '0'); elsif (clock='1' and clock'event) then if load = '1' then Q_tmp <= I; end if; end if; end process; -- concurrent statement Q <= Q_tmp; end register_2bit_arch; ----------------------------------------------------

----------------------------------------------------

 Final Entity
library ieee ; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;

entity final is port( read1: in std_logic; write1: in std_logic; input1: in std_logic_vector(1 downto 0); output1: out std_logic_vector(1 downto 0); empty: inout std_logic; overflow: inout std_logic; clk: in std_logic ); end final;

architecture final_arch of final is component mux_4x1 is port( I3: I2: I1: I0: S: O: in std_logic_vector(1 downto 0); in std_logic_vector(1 downto 0); in std_logic_vector(1 downto 0); in std_logic_vector(1 downto 0); in std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0)

); end component;

 Contd
component up_down_counter is port(clk, rst_a, mode_r,mode_w : in std_logic; --mode=1 up counting, mode=0 down counting q : out std_logic_vector(1 downto 0)); end component;

component counter_4 is generic(n: natural :=2); port( clock: in std_logic; clear: in std_logic; count: in std_logic; Q: out std_logic_vector(n-1 downto 0) ); end component; component DECODER_2x4 is port( I: in std_logic_vector(1 downto 0); O: out std_logic_vector(3 downto 0) ); end component; component comparator_2bit is port( iwrite: in std_logic_vector(1 downto 0); iread: in std_logic_vector(1 downto 0); equal: out std_logic ); end component;

 Contd
component register_2bit is generic(n: natural :=2); port( I: clock: load: clear: Q: ); end component; in std_logic_vector(n-1 downto 0); in std_logic; in std_logic; in std_logic; out std_logic_vector(n-1 downto 0)

--signal signal write_counter_output: std_logic_vector(1 downto 0); signal read_counter_output: std_logic_vector(1 downto 0); signal write_decoder_output: std_logic_vector(3 downto 0); signal reg0_output: std_logic_vector(1 downto 0); signal reg1_output: std_logic_vector(1 downto 0); signal reg2_output: std_logic_vector(1 downto 0); signal reg3_output: std_logic_vector(1 downto 0); signal total_counter_output: std_logic_vector(1 downto 0); signal error_comparator_output: std_logic; signal read2 :std_logic; signal write2: std_logic;

 Contd
read_counter: counter_4 port map( clock=>clk, clear=>'1', count=> read2,Q=>read_counter_output); read_mux: mux_4x1 port map( I3=>reg3_output write_counter: counter_4 port map( clock=>clk, clear=>'1', ,I2=>reg2_output,I1=>reg1_output,I0=>reg0_output,S=>read_co count=> write2,Q=>write_counter_output); unter_output,O=>output1); write_decoder: decoder_2x4 port map(I=>write_counter_output, total_counter: up_down_counter port map(clk=>clk, rst_a=>'0', O=>write_decoder_output); mode_r=>read1, mode_w=>write1,q=>total_counter_output); begin reg0: register_2bit port map(I=>input1,clock=>clk,load=>write_decoder_output(0),clear= >'1', Q=>reg0_output); reg1: register_2bit port map(I=>input1,clock=>clk,load=>write_decoder_output(1),clear= >'1', Q=>reg1_output); reg2: register_2bit port map(I=>input1,clock=>clk,load=>write_decoder_output(2),clear= >'1, Q=>reg2_output); reg3: register_2bit port map(I=>input1,clock=>clk,load=>write_decoder_output(3),clear= >'1', Q=>reg3_output); process(total_counter_output,read1,write1) begin empty<= ( (not total_counter_output(1)) and (not total_counter_output(0))); overflow<= (total_counter_output(1) and total_counter_output(0)); end process; process(empty,overflow,read1,write1) begin read2<= read1 and (not empty); write2<=write1 and (not empty); end process;

end final_arch; --------------------------------------------