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5/2/2014
What is an Interrupt ?
A hardware interrupt is a CPU facility which permits spurious asynchronous events to suspend program execution and instead execute a software module to service the event.
The connection to the processor which allows external devices to signal a request for service is called an interrupt pin. The software module that the processor executes in response to an interrupt is called an interrupt service routine ( ISR ). The interrupt mechanism is such that after completion of the ISR the processor returns to execution of the main program from the point at which it was interrupted.
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A maskable interrupt, if asserted, will only interrupt the processor if it is enabled ( unmasked ). Maskable interrupts can be enabled ( unmasked ) or disabled ( masked ) by software.
Most maskable interrupts automatically become disabled (masked) after an interrupt has occurred. It requires further software commands to re-enable maskable interrupts.
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Interrupt Priority
For processor with multiple interrupt input pins, the various interrupts are assigned a priority. When simultaneous interrupts occur the highest priority interrupt will be serviced before lower priority interrupts. It is possible to arrange software such that whilst a lower priority interrupt is being serviced that a higher priority interrupt can interrupt the lower priority service routine.
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8085A Interrupts
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Trigger Type Rising Edge AND High Level Rising Edge High Level High Level High Level
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For example to enable RST 7.5 and RST 5.5 and disable RST6.5
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ORG 0000H JMP START ORG 0034H JMP ISR65 ORG 003CH JMP ISR75
START: . MVI A, 00011010B SIM EI .. .. ISR65: .. .. RET ISR75: .. .. RET
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The choice of opcode is restricted as it is necessary to automatically save the contents of the program counter to enable the program to return to the point in the software where it was interrupted.
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Following decoding of the call opcode, the processor executes a further two interrupt acknowledge machine cycles to fetch the address of the start of the ISR.
It is incumbent on the interrupting device to place the low byte of the address of the ISR onto the data bus in response to the second INTA* control signal and the high byte of the address in response to the third INTA* signal.
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The next instruction the processor will execute will be the first instruction of the ISR.
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((SP)-2) (PCL)
((SP) (PC) (SP) 2 8*n
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