Interconnect

Earlier transistors were relatively slow

Interconnect wires were wide and thick thus
resistance was very low

Scenario changed in modern VLSI designs
many layers of wires
wire RC delay exceeds gate delay
cross talk
on-chip interconnect inductance

Engineering the wires is challenging !!
Wires are as important as transistors
Speed
Power
Noise
Alternating layers run orthogonally

Interconnect cont..
90 nm
45 nm
M8
M6
Wire Geometry
Wire Geometry
Pitch = w + s
Aspect ratio: AR = t/w
Old processes had AR <<
1
Modern processes have
AR 2
Pack in many skinny wires

l
w s
t
h
Intel 45 nm metal layers
Wire Resistance
r = resistivity (W*m)
l
w
t
R
Wire Resistance
r = resistivity (W*m)
l
w
t
l
R
t w
r

Wire Resistance
r = resistivity (W*m)


R

= sheet resistance (W/)

is a dimensionless unit(!)
Count number of squares
R = R

* (# of squares)
l
w
t
1 Rectangular Block
R = R (L/W) W
4 Rectangular Blocks
R = R (2L/2W) W
= R (L/W) W
t
l
w w
l
l l
R R
t w w
r

Choice of Metals
Until 180 nm generation, most wires were aluminum
Modern processes often use copper
Cu atoms diffuse into silicon and damage FETs
Must be surrounded by a diffusion barrier
Metal Bulk resistivity
(mW*cm)
Silver (Ag) 1.6
Copper (Cu) 1.7
Gold (Au) 2.2
Aluminum (Al) 2.8
Tungsten (W) 5.3
Molybdenum (Mo) 5.3
Sheet Resistance
Typical sheet resistances in 180 nm process
Layer Sheet Resistance (W/)
Diffusion (silicided) 3-10
Diffusion (no silicide) 50-200
Polysilicon (silicided) 3-10
Polysilicon (no silicide) 50-400
Metal1 0.08
Metal2 0.05
Metal3 0.05
Metal4 0.03
Metal5 0.02
Metal6 0.02
Capacitance
Parallel plate capacitance, fringing capacitance,
capacitance with a neighbor
Capacitance Trends
Parallel plate equation: C = eA/d (simple model)
Wires are not parallel plates, but obey trends
Increasing area (W, t) increases capacitance
Increasing distance (s, h) decreases capacitance
Dielectric constant
e = ke
0
e
0
= 8.85 x 10
-14
F/cm
k = 3.9 for SiO
2
Processes are starting to use low-k dielectrics
k 3 (or less) as dielectrics use air pockets
Different models are used to incorporate fringing field capacitance also.

Capacitance models
The total capacitance is assumed
to be the sum of a parallel plate
capacitor of width w t/2
and
a cylindrical capacitor of radius t/2.
Isolated wire
Wire Capacitance
Wire has capacitance per unit length
To neighbors
To layers above and below
C
total
= C
top
+ C
bot
+ 2C
adj
layer n+1
layer n
layer n-1
C
adj
C
top
C
bot
w s
t
h
1
h
2
Capacitance of M2 line as a function of
width and spacing
Typical wires have ~ 0.2 fF/mm
Compare to 2 fF/mm for gate capacitance
0
50
100
150
200
250
300
350
400
0 500 1000 1500 2000
C
t
o
t
a
l
(
a
F
/
m
m
)
w (nm)
Isolated
M1, M3 planes
s = 320
s = 480
s = 640
s=
8
s = 320
s = 480
s = 640
s=
8
Diffusion & Polysilicon
Diffusion capacitance is very high (about 2
fF/mm)
Comparable to gate capacitance
Diffusion also has high resistance
Avoid using diffusion runners for wires!
Polysilicon has lower C but high R
Use for transistor gates
Occasionally for very short wires between
gates
Lumped Element Models
Wires are a distributed system
Approximate with lumped element models







3-segment p-model is accurate to 3% in simulation
L-model needs 100 segments for same accuracy!
Use single segment p-model for Elmore delay
C
R
C/N
R/N
C/N
R/N
C/N
R/N
C/N
R/N
R
C
L-model
R
C/2 C/2
R/2 R/2
C
N segments
p-model T-model
Example
Metal2 wire in 180 nm process
5 mm long
0.32 mm wide
Construct a 3-segment p-model
R

=
C
permicron
=
Example
Metal2 wire in 180 nm process
5 mm long
0.32 mm wide
Construct a 3-segment p-model
R

= 0.05 W/ => R = 781 W

C
permicron
= 0.2 fF/mm => C = 1 pF
260 W
167 fF 167 fF
260 W
167 fF 167 fF
260 W
167 fF 167 fF
Inductance
Inductance is difficult to extract and model, so
engineers prefer to design in such a way that
inductive effects are negligible.
But in high speed designs inductance effect
need to be considered
Currents flowing around a loop generate
magnetic field proportional to the area of the
loop and the amount of current
Even if the Resistance of the wire is zero and
therefore zero RC delay,
Flight-time along a wire of length with inductance and
capacitance per unit length of L and C is
Changing magnetic fields in turn produce
currents in other loops. Hence, signals on
one wire can inductively couple onto another;
this is called inductive crosstalk.
In other words, signals travel about half the speed of light.
Using low-k (< 3.9) dielectrics raises this velocity.
Inductance
Skin effect
Skin effect is the tendency of
an alternating electric current (AC) to
become distributed within
a conductor such that the current
density is largest near the surface of the
conductor, and decreases with greater
depths in the conductor.
The electric current flows mainly at the
"skin" of the conductor, between the outer
surface and a level called the skin depth.
= resistivity of the conductor
= angular frequency of current = 2
frequency
= absolute magnetic permeability of the
conductor

Skin depth
Frequency can be estimated as
Skin depth
where t
rf
is the average 2080% rise/fall time.
If min(w, t) >2, part of the
conductor carries no current and the
resistance increases.
Delay
Energy
Cross talk
Inductive effects

Interconnect impact
Delay impact

the wire capacitance adds loading to each gate
long wires have significant resistance that contributes
distributed RC delay (flight time)

Interconnect impact
Interconnect impact-delay
In this figure, gate is represented as a voltage source with effective
resistance R1.
The two receivers are located at nodes 3 and 4, in which node 3 is
longer and is represented with a pair of segments,
while node 4 is represented with a single segment.
Elmore delay from x to each receiver,
TD
3
= R
1
C
1
+(R
1
+R
2
)C
2
+(R
1
+R
2
+R
3
)C
3
+R
1
C
4
TD
4
=R
1
C
1
+R
1
(C
2
+C
3
)+(R
1
+R
4
)C
4

Wire switching energy is determined by the
capacitance.
So as interconnect wire capacitance increases,
energy required for switching will also be
increased.
Suppose C
permicron
=0.2 fF/m
Energy per unit length (mm) to transmit 1 bit of
information is

0.2pF/mm*(1.0)
2
=0.2 pJ/bit/mm.
(0.2 mW/Gbps.)
Interconnect impact-energy
Consider a microprocessor on a 20 mm 20 mm die
running at 3 GHz in the 65 nm process. A layer of
metal is routed on a 250 nm pitch. Half of the
available wire tracks are used. The wires have an
average activity factor of 0.1. Determine the power
consumed by the layer of metal.
Interconnect impact-delay
Crosstalk
Capacitances to adjacent neighbor and ground
1. Cross talk delay effects
2. Cross talk noise effects
Crosstalk
A
B
If A switches but B does not, V = V
DD
. C
eff
(A)=C
gnd
+C
adj
If A and B switches in the same direction, V = 2V
DD
.
Ceff(A)=Cgnd+2Cadj
If both A and B are switches in the same direction V = 0.
Ceff(A)=Cgnd and Cadj is effectively absent for delay calculations
Crosstalk noise
Suppose wire A switches while B is
supposed to remain constant.
Victim noise =>
Floating
Crosstalk noise
If victim is actively driven, driver will supply
current to oppose the noise
Inductive effects
set of wire lengths for which inductance is
relevant
Models of clock line as a 5 stage section
Inductive effects
5 mm-long clock line, above a ground plane driving a 2 pF clock
load. If its width is 4.8 m and thickness is 1.7 m, it has
resistance of 4 /mm, capacitance of 0.4 pF/mm, and
inductance of 0.12 nH/mm.
Inductive effects
Response of RC model and RLC model to an ideal voltage
source with 80 ps rise time
Interconnect engineering
Width, spacing and layer can be optimized
to reduce the interconnect delay
Minimum pitch for non-critical interconnections for better
bandwidth and density.
if wire capacitance dominates -increase spacing which
reduces capacitance and also reduces energy and
coupling noise.

if delay due to wire resistance is more -widening the wire
reduces resistance and thereby delay.

Wire geometry
Wire thickness depends on choice of
metal layer
Upper layers are thicker for handling more
current

Lower layers will have tight pitch

Repeaters

Wire without repeater
Wire with repeater
Equivalent circuit of a
segment
After differentiating,
Crosstalk control
Increase spacing to adjacent lines
Shield wires
Ensure neighbors switch at different times
Crosstalk cancellation
Wire shielded on one side
Wire shielded on both sides
Interleaved
Low swing signaling
Wire is allowed to swing only in a lower
range rather than waiting for the full
voltage swing
driver is turned off after the output has
swung sufficiently
dynamic power is reduced
complex driver and receiver units are
required
The power consumption for low-swing signaling depends
on both the driver voltage V
drive
and the actual voltage
swing V
swing
.

Dynamic power dissipation
Challenges
synchronous low-swing signaling
technique
The system clock for both driver and receiver
Wire equalization
Driver 1
Drver 2 (SA-F/F)
Regenerators/boosters
Not just like repeaters-which are limited to unidirectional busses
Regenerators placed in parallel with wires
Generally skewed gates are used
HI skew gates favors rising output
LO skew gates favors a falling output