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4



Insert image
here
Insert image
here
Insert image
here
IGCT Training

Ren Ernst
Sales Engineer

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Contents
Principle of operation
Basic Topologies
Design criteria for VSI
VSI clamp circuit design
Applying IGCT gate unit
Series connection

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Introduction to IGCTs

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Electronic Switches
Thyristor
Can be turned on by gate signal but can only be turned off by
reversal of the anode current
Gate Turn-Off Thyristor (GTO)
Can be turned on and off by the gate signal but requires large
capacitor (snubber) across device to limit dv/dt
Transistors (transitional resistor)
Can be turned on and off by the gate (or base) signal but has
high conduction losses (its an amplifier, not a switch)
Integrated Gate Commutated Thyristor (IGCT)
Can be turned on and off by the gate signal, has low conduction
loss and requires no dv/dt snubber

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IGCT model
Two-transistor Regenerative Switch model of a GTO
K
CATHODE
GATE
ANODE A A
K
G
G
I
a
I
k

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Principle of IGCT Operation
P
N
P
N
Anode
Cathode
Gate
I
AK
I
GK
P
N
P
N
Anode
Cathode
Gate
- V
GK
V
AK
Conducting Thyristor Blocking Transistor

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Hard Turn-off mode
anode current
gate current
U
GK
t
comm
t
desat
U
AK
U
AK
, I
A
, I
G
t
U
GK
t
Snubber less operation => tdsat > 0

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IGCT Turn-off
4
1
I
a

(kA)
V
dm
T
j
= 90C
I
tgq
4
3
2
1
0
-10
-20
V
g
(V)
2
3
0
anode voltage V
d
anode current
I
a
gate voltage
V
g

thyristor transistor
x
starts to block
V
d
(kV)
20 15 30 25 35 t ( s)

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Thermal distribution

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IGCT = GTO + IGBT?
GTOs
low cost device
high reliability
IGBTs
low cost circuit
fast switching
IGCTs
lowest cost device
lowest cost circuit
highest reliability
fastest switching
highest efficiency

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Turn off capability GTO <=> IGCT
7
0
1
2
3
4
5
6
0 1 2 3 4 5 6
Snubber Capacitance (uF)

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Basic Topologies
V
R

S
3

S
4

S
5

S
6

S
1

S
2

L
s

L
C
clamp
D
clamp

R
FWD
6

Clamp
Network
S
5
S
3
S
1

S
6
S
2
S
4

V
D
C

FWD
1

IGCT Inverter
IGBT Inverter

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GTO, IGBT and IGCT phase-legs
IGBT
GTO
IGCT
Schematics

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Application Specific Asymmertric IGCT
10
12
14
16
18
20
22
24
26
28
30
1.50 1.70 1.90 2.10 2.30 2.50 2.70 2.90 3.10 3.30 3.50
VT @ 3.3kA, 125C [V]
E
o
f
f

@

2
.
8
k
V
,

3
.
3
k
A
,

1
2
5

C

[
W
s
]
homogeneous lifetime engineering
local lifetime engineering
12
10
11
Technology curves of asymmetric 4 kA / 4.5 kV IGCT's
Type 12: Low on-state losses
Type 10: Low total losses
Type 11: Low switching losses

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Overview 4.5 kV asymmetric IGCT
Type low on-state
losses
(Type 12)
low total losses
(Type 10)
low switching losses
(Type 11)
Part N 5SHY 35L4512 5SHY 35L4510 5SHY 35L4511
Junction temp.
range
-40C 125C -40C 125C 10C 125C
V
TM
@ 4 kA, 125C 2V 2.7 V 3.5 V
E
OFF
@ 4 kA, 2.8 kV,
125C
37 Ws 22 Ws 17 Ws
Typical application AC/DC breakers
(SSB)
Traction,
Energy Management
High Frequency
MVDs

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-3000
-2000
-1000
0
1000
2000
3000
4000
5000
-0.5 0 0.5 1 1.5 2 2.5 3
t [s]
U
A
K
,

I
A

[
V
,

A
]
-3.00E+01
-2.00E+01
-1.00E+01
0.00E+00
1.00E+01
2.00E+01
3.00E+01
4.00E+01
5.00E+01
U
G
K

[
a
.
u
.
]
Tj= 25C
Tj = 125C
U
AK
(25C)
U
AK
(125C)
U
GK
n
n
p
p
n
n
p
p
n
n
p
p
n
n
p
p
o
t(25C)
o
t(125C)
Snubberless Operation

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Turn-off waferforms at different temperatures
0
1000
2000
3000
4000
8 9 10 11
t [s]
U
A
K
,

I
A
,

[
V
,

A
]
Tj = 125C
Tj = 75C
Tj = 25C
U
AK
I
A
IGCT type 5SHY 35L4511

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Turn-off waferforms @ Tj = 125C
0
1000
2000
3000
4000
6 8 10 12 14
t [s]
I
A
,

U
A
K
,

[
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,

V
]
4510
4511
4512
I
A
U
AK
Signifficant reduction of tail current

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Turn-off waveforms = f(Tj)
0
1
2
3
4
5
kV
0
1
2
3
4
5
kA
40 60 80 100
s
ITGQ = 3200 A
VDM= 3470 V
VDC = 2800 V
0
1
2
3
4
5
kV
0
1
2
3
4
5
kA
40 60 80 100
s
VDM = 4280 V
ITGQ = 3250 A
VDC = 2800 V
5SHY 35L4510 @ Tj = -40C
5SHY 35L4510 @ Tj = 125C

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Simple GCT Construction

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VSI Test Circuit
L
CL
L
i
R
s
DUT
L
Load
C
CL
V
LC

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VSI test circuit waveforms
CS CS
I
T
V
DSP
V
DM
V
D
V
G
t
don
I
T
I
TM
di/dt
0.9 V
D
0.1 V
D
V
D
Turn-on Turn-off
V
G
t
r
t
doff
t
don1
SF
SF
0.4 I
TGQ

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VSI test circuit parameters
Design these parameters to IGCT and diode capability:
Stray inductance, L
CL

di/dt limiting inductor, L
I

Clamping capacitor, C
CL

Clamping resistor, R
S

These parameters are normally given by converter
system design and does not normally influence IGCT
performance or design:
DC link capacitor, C
DC

Load inductor, L
LOAD

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Design criterions for di/dt limiting inductor
Component di/dt capability (SOA)
IGCT
Diode

Maximum surge current capability
determined by L
I
and C
DC


Diode switching losses
Losses increase when L
I
value reduce

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Component di/dt capability
GCT di/dt capability:
very high (compared to GTO) due to hard driven principle.
very high turn-on pulse di/dt ( >500A/us) ensures homogeneous,
robust and lossless turn-on.
More than 3000A/us has been applied in application.
Diode di/dt capability:
Mostly the limiting part in IGCT VSI design
This is especially true for snubberless applications which has
become standard in the market.
Typical values are between 200 and 1000 A/us dependent on
wafer size and maximum required switching voltage.

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di/dt limiting inductor value
In VSI topologies, the diode turn-off di/dt capability
mostly determines the size of the di/dt choke.
L
i
> (V
dc
/(di/dtmax))
A bigger inductor value might be chosen in order to limit
switching losses of the diode or to limit the surge current
stress during shoot-through in a phase leg.

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Stray inductance design
The stray inductance, L
CL
, significantly influence
IGCT turn-off SOA and losses
Diode turn-off SOA and losses
Diode snap behaviour at low turn-off currents
Snap overvoltage
Noise emission due to high frequency oscillations
If L
CL
data sheet values are exceeded, SOA and
specified turn-off losses are not valid.

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Turn-off losses versus stray inductance
V300 V800 V1500 I_300 I_800 I_1500
0
1
2
3
4
kV
0
1
2
3
kA
2 4 6 8 10 12 14
s
Variation der Clampinduktivitt: 300nH / 800nH / 1500nH
Testbedingungen:
Tj= 125C
ITGQ= 3000A
El. Typ= 5SGY35L 4510 allg. Bedingungen: Vzk = 2kV
Ls = 3.7H
Ls2 = 1.5H
Rs = 0.5 Ohm
Ccl = 7.6 F
Dcl, Df = 5SDF10H4502
V300 V800 V1500 I_300 I_800 I_1500
P300 P800 P1500 e300 e800 e1500
0.00
0.75
1.50
2.25
3.00
3.75
4.50
kV
0.0
0.5
1.0
1.5
2.0
2.5
3.0
kA
0
2
4
6
8
10
12
MW
0
4
8
12
16
20
24
J
5 10 15
s
Eoff = f(Ls) Clampinduktivitt: 300nH / 800nH / 1500nH
Testbedingungen:
Tj= 125C
ITGQ= 3000A
El. Typ= 5SGY35L 4510 allg. Bedingungen: Vzk = 2kV
Ls = 3.7H
Ls2 = 1.5H
Rs = 0.5 Ohm
Ccl = 7.6 F
Dcl, Df = 5SDF10H4502

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The RLC clamp circuit
Analysis of damped parallel resonance circuit comprising
L
I
, C
CL
and R
S
allows for an initial determination of C
DC

and R
S
values.
This analysis yield a reasonably good result when
C
DC
>> C
CL

Stray inductances are small (L
S1
, L
S2
)
L
LOAD >>
L
I

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VSI test circuit again - more details
Czk
Ls
0 O
Ls2
Uzk
Dcl
Prfling
Rs
Ls1
Ccl
GCT
DQ
Last
Prfling
Diode
I

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RLC circuit - 2. Order differential equation
Differential equation:
L
I
C
CL *
(di
L
/dt)
2
+ (L
I
/ R
S
)
*
(di
L
/dt) + i
L
= 0 (1)
Damping factor:
D = ( L
I
/ C
CL
)/(2R
S
)

D ~ 0.8 (2)
Clamping capacitor:
C
CL
> (L
I

*
D
4
*
I
L
)/(K
1*
V
CL
)

K
1
~ 0.9 (3)
Damping resistor:
R
s
= ( L
i
/ C
cl
)/(2D)

(4)

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RLC circuit - why damping resistor?
To allow clamping capacitor to discharge before next
switching transition (switching overvoltages does not
add up to exceed component ratings).
Limit switching voltage overshoot V
DM
Prevent current flowing in clamping diode after switching
transition due to additional oscillations in RLC circuit
(slightly undercritical damping - see formula 2)
Value obtianed with formula (4)

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RLC circuit - the clamping capacitor
Value obtained through formula (3) where
C
CL
> (L
I

*
D
4
*
I
L
)/(K
1*
V
CL
)

K
1
~ 0.9 (3)
D is damping factor (formula (2))
I
L
< I
TGQM
- maximum turn-off current of the application which
has to be lower than maximum controllable turn-off current of
the device according to specification
V
CL
= V
DM
- V
DCMAX
which is the difference between the
maximum allowed peak voltage and the maximum required dc
link voltage of the application
K
1
- this factors accounts for the influence of the stray
inductance, L
S2
, which is never zero although kept as low as
possible

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Block diagram - AC input
Tx
Logic
Monitoring
Turn-
Off
Circuit
Turn-
On
Circuit
20VDC
Status Feedback
(Light)
Gate
Kathode
24 ... 40VAC
or
24 ... 40VDC
Rx
Command Signal
(Light)
Internal Supply
LEDs
Stabilizer
Supply
Anode
Monitoring
Anode
For IGCT part numbers:
AS-IGCT: 5SHY 35L451x
RB-IGCT: 5SHZ 08F6000

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Power up - AC input
AC input: Inrush current of about 9 A flows during about 150 ms.
Gate drive has current limiter on the board.








DC input: Gate drive does not provide inrush current limitation

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Isolation interface
The isolation requirements appears as a function of the
maximum applied voltage of the specific application
Also the supplied power to the gate drive varies from
project to project
Consequently isolation transformer is difficult to
standardize

Gate drive has no onboard isolation transformer!

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Optical interface - receiver
Receiver for command signal
Agilent, Type HFBR-2528
P
on CS
Optical input power > -21 dBm
Valid for 1mm plastic optical fibre (POF)

P
off CS
Optical noise power < -40 dBm

t
GLITCH
Pulse width threshold s 400 ns
Max. pulse width without response

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Optical interface - transmitter
Transmitter for status feedback
Agilent, Type HFBR-1528

P
on SF
Optical output power > -19 dBm

P
off SF
Optical noise power < -50 dBm

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Turn-on circuitry
V1
V2
D1
L1
D3
K
G
C
20V
0V
V3
D2
L2
Turn on delay time: 2.75 - 2.85 us
Less than 100 ns spread of delay
time


CH4: Command signal (HIGH: light)
CH2: Turn-on current
CH1: V
GK

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Turn-off circuit
V6
K
G
C
20V
0V
OFF
Turn off delay time: 2.75 - 2.85 us

Less than 100 ns spread of delay
time






CH4: Command signal
(HIGH: light)

CH1: V
GK


CH2: On-state current
[20 A/Div]

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On-state: Back-porch current circuit
V4
C
20V
0V
K
G
L3
L4
C1
V5
GHK
CH4: Command signal (HIGH: light)
CH2: Back porch current
[5 A/Div]
Chopper in current control
mode

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On-state: Re-triggering (external)
CH4: Command signal (HIGH: light)
CH1: V
GK
CH2: Turn-on current
50 A/Div

Re-firing of turn-on pulse can be commanded via command input

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On-state: Re-triggering (internal)
CH1: V
GK

CH2: Turn-on current
[50 A/Div]

Gate voltage detection also controls re-triggering of turn-on pulse

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Power consumption (1): transferred power
P
transfer
= V
gint*
Q
gq
(I
tgq
)
*
f
s
V
gin
: internal regulated voltage
Q
gq
(I
tgq
) : charge transferred to the power circuit
f
s
: switching frequency
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
0 200 400 600 800 1'000 1'200 1'400
Itgq [A]
P
g
q

[
W
]
50Hz
500 Hz
1000 Hz

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Power consumption (2): dissipated power
0
5
10
15
20
25
30
35
0 200 400 600 800 1000
Switching frequency [Hz]
p
o
w
e
r

[
W
]
0.1
0.5
1
duty cycle:
Standby
Turn-on pulse
Back porch current

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6

-

Thermal management
Calculated lifetime of on-board capacitors 20 years.
With slightly forced air cooling (air velocity > 0.5 m/s).
Strong air cooling allows for increased ambient temperature.





0
500
1000
1500
2000
2500
3000
250 350 450 550 650 750 850 950
F
S
[Hz]
I
TGQ(AVG)
[A]
T
amb(max)
= 40 C
T
amb(max)
= 50 C
Limits for full lifetime
operation for 5SHY 35L4510

A
B
B

S
w
i
t
z
e
r
l
a
n
d

L
t
d


-

4
7

-

Diagnostics: Status feedback
O
p
t
i
c
a
l
C
o
m
m
a
n
d
S
i
g
n
a
l
I
n
p
u
t
G
a
t
e

t
o
c
a
t
h
o
d
e
v
o
l
t
a
g
e
S
u
p
p
l
y
v
o
l
t
a
g
e
O
p
t
i
c
a
l
S
t
a
t
u
s
F
e
e
d
b
a
c
k
o
u
t
p
u
t
G
a
t
e

d
r
i
v
e
s
t
a
t
u
s

L
E
D
s
CS Status GK Status V
Gint
SF
HIGH ON OK Inverse input signal
CS
OK Power OK, Gate ON
HIGH OFF
(t
off
<10us)
OK Inverse input signal
CS
OK Power OK, Gate ON
HIGH OFF
(t
off
>10us)
Dont care CS FAIL Power OK, Fault
HIGH Dont care FAIL CS FAIL Fault
LOW OFF OK Inverse input signal
CS
OK Power OK, Gate OFF
LOW ON Dont care CS FAIL Power OK, Gate ON, Fault
LOW Dont care FAIL CS FAIL Gate OFF, Fault

A
B
B

S
w
i
t
z
e
r
l
a
n
d

L
t
d


-

4
8

-

Diagnistics: Fault conditions
Loss of power supply
On state hold-up time (no switching): >300 ms
Off state hold-up time (no switching): >500 ms
Open circuit gate
Supply overvoltage
Short circuit gate

A
B
B

S
w
i
t
z
e
r
l
a
n
d

L
t
d


-

4
9

-

Diagnostics: LED display
P
o
w
e
r

O
K

(
G
r
e
e
n
)
F
a
u
l
t

(
R
e
d
)
G
a
t
e

O
N

(
Y
e
l
l
o
w
)
G
a
t
e

O
f
f

(
G
r
e
e
n
)

A
B
B

S
w
i
t
z
e
r
l
a
n
d

L
t
d


-

5
0

-

EMI testing: dv/dt stress
Amplitude: 3 kV
dv/dt: 13 kV/us

A
B
B

S
w
i
t
z
e
r
l
a
n
d

L
t
d


-

5
1

-

EMI testing: di/dt stress

A
B
B

S
w
i
t
z
e
r
l
a
n
d

L
t
d


-

5
2

-

EMI testing: di/dt stress

A
B
B

S
w
i
t
z
e
r
l
a
n
d

L
t
d


-

5
3

-

Vibration compliance: Test set-up

A
B
B

S
w
i
t
z
e
r
l
a
n
d

L
t
d


-

5
4

-

Vibration compliance: Test parameters
IGCT meets IEC standard IEC 61373

A
B
B

S
w
i
t
z
e
r
l
a
n
d

L
t
d


-

5
5

-

Series connection with RC-snubber (1)

A
B
B

S
w
i
t
z
e
r
l
a
n
d

L
t
d


-

5
6

-

Series Connection with RC-snubber (2)
Design Trade-offs for RC-snubber
Dynamic turn-off voltage deviation:
doff TGQ
t I
Cs
V A - - = A
1