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• 80286 16 bit µp
• 16 Mbytes physical memory
• Multi-user
• Multitasking
• OS
• User protection
• Virtual memory management
80286 - Architecture
• The bus unit – BU
– Performs all memory and i/o reads and writes, pre-fetches instruction
bytes and controls transfer of data to and from processor extension
devices such as the 80287 math coprocessor.
• Flag reg.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X NT IO PL O D I T S Z X Ac X P X Cy
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS EM MP PE
Order Interrupt
1 Instruction exception
2 Single step
3 NMI
4 Processor extension segment overrun
5 INTR
6 INT instruction
80286 Real Address Mode Operation
• After the 80286 is reset, it starts executing in its real address
mode.
• MS-DOS systems operates in Real Address Mode
• In this mode 80286 can address up to 1MB of physical
memory.
• Interrupt Vector Table of the 80286 is located in the first 1KB
of memory. (from address 00000h to 003FFh ).
• The addresses from FFFF0h to FFFFFh are reserved for
system initialization.
• Functions performed in this mode:
– It initializes the IP and other registers of 80286
– Initializes the peripheral
– Enables interrupts
– Sets up descriptor tables
– Prepares for entering the protected virtual address mode.
Protected Virtual Address Mode Operation (PVAM)
• The 80286 is able to address 1Gbyte if virtual memory per
task.
• Swapping
• Unswapping
• Program is divides into Segments or pages
• Segments or pages have been associated with a data
structure called as a descriptor.
• Descriptor contains
– segment base address,
– segment limit,
– segment type,
– privilege level,
– segment availability in physical memory,
– descriptor type and
– segment use by another task.
• Descriptor table.
Descriptors and Their Types
Special types of descriptors which are used to carry out additional functions
like
– Transfer of control
– Task switching
1. Data segment descriptors
2. System segment descriptors
– Store system data and execution state of a task for multitasking
system.
3. Gate descriptors
– The gate descriptors control the access to entry points of the
code to be executed.
4. Interrupt descriptors
– These are used to store task gates, interrupt gates and trap
gates.
• Halt
• Instruction Unit
1. 16-byte instruction code queue
2. 3-byte instruction decoded queue
3. The barrel shifter increases the speed of all shift and rotate operations
• INTR :
• NMI :
• RESET :
VM Flag : If this is set, 80386 enters the virtual 8086 mode within the
protected mode
RF-Resume flag : This is used with the debug register breakpoints, i.e. any
debug fault is ignored during the instruction cycle.
Addressing Modes:
Data Types
• Bit
• Bit field
• Bit string
• Signed byte
• Unsigned byte
• Offset
• Pointer
• BCD
• Packed BCD
• Character
• Strings
Descriptors tables
• LDT
• GDT
• IDT, etc
Control registers
• CR0,CR2,CR3
– Load, store instructions are available to access these
registers.
Modes
1. RAM
1. After reset FFFF FFF0h under the RAM
2. Interrupt Vector table – 0000 003FFh -- 1KB
2. PROTECED MODE
1. 4-GB --- PA
2. 64-TB --- virtual memory/task
Real Addressing Mode – physical address
Physical Address formation in Protected mode
4
Virtual 8086 mode
PENTIUM PROCESSOR
• The Pentium processor has 237 pins, arranged in a pin
grid array (PGA)
HYBRID ARCHITECTURE
– RISC AND CISC CONVERGENCE
– Pentium and Athlon family of processors
– SIMD : single Instruction Multiple Data
• The Advantages of RISC
– RISC instructions, being simple, can be hard-
wired
– Processor can work at a high clock frequency
and thus yields higher speed.
– On-chip MMU, Floating point arithmetic units.
– Chip cost is low
– More devises can place on chip
– Compilers produce more efficient codes in
RISC µp
– Loading and decoding of instructions in a
RISC processor is simple and fast.
Design issues of RISC processor
• Register Windowing
• Massive Pipelining
• Single cycle instruction execution