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Outline

• Macrocell,megacell
• Intellectual property
• Semi custom design flow
• Array Based Implementation
Approaches
Macrocell,Intellectual
Property
• Macrocell: It is a complex cell which is
more excellent then standard cell.
• Standardizing at the logic gate level is
attractive for random logic functions
but it turns out to be inefficient for
more complex structures such as
multipliers,memories and embedded
up and DSPs.
• So,we need macrocell which is high
efficient cell.
Two type of macrocells
• (1)Hard Macro (2)Soft Macro
• (1)Hard Macro:
• Represents a module with given functionality and
predetermined physical design.
• Relative location of transistor and wiring within the module
is fixed.
• Hard Macro can be parameterized a generator called the
module compiler,is used to create the actual physical
layout.
• Generator module also provides accurate timing and power
information.
• Contribution of the macrocell generator is to translate the
compact input description into optimized connection of
standard cells that meet the timing constraints.
Hard macrocell
• It is parameterized which means that versions with slightly
different properties are available or can be generated.
• Eg. Multiplier & memories.
• Embedded memory & up are good example of hard macro
• Hard multiplier macro may not only genarate 32*16
multiplier but also 8*8 one.
• Advantage:
• It has a all good properties of custom design:dence
layout , optimized and predictable performance ,power
dissipation
• Encapsulating function into macro module it can be reused
over and over in different designs.this reuse helps to offset
the initial design cost.
Hard macrocell
• Disadvantage:
• For every new technology, a major
redesign of the block is necessary.
Soft macrocell
• Module with given functionality,but
without a specific physical
implementation
• Placement and wiring of a soft macro
may vary from instance to instance
• Timing data can only be determined
after the final synthesis and
placement and routing steps.
Soft macrocell
• Advantage:
• It support a wide range of technologies
and processes. So it reduce design cost
over a wide set of design.
• Genarator exploits its knowledge of the
function under consideration to
overcome with clever structures that
are more efficient.
• Module with different aspect ratio can
easily be generated.
Intellectual property
• Modules are acquired from third party vendors,
who make the function available through royalty
or licensing agreements.
• Macromodules distributed in this style are called
intellectual property(IP) modules.
• Eg.embedded up & uc ,DSP processors, MPEG
decoding and encoding for video.
• IP module not only deliver the hardware but it
also has to come with appropriate software tools.
Semi Custom Design
Flow
• Design Capture :
• It enter the design into the ASIC design system
• A variety of method can be used to do so,including
schematic and block diagram;Hardware
descriptive languages such as VHDL, verilog and c
derivative.
• Logic synthesis :
• it is a tool which translate module describe using
an HDL language into netlist. Netlist of reused or
generated macros can then be inserted to form
complete netlist of the design.
Semi Custom Design
Flow
• Prelayout Simulation and Verification :
• The design is check for correctness.performance analysis
is performed based on estimated parasitics and layout
parameters.if the design is found to be nonfunctionl,extra
iterations over the design capture or the logic synthesis is
necessary.
• Floor Planning :
• Based on estimated module size ,the overall outlay of the
chip is created.the global power and clock distribution
networs also are conceived at that time.
• Placement :
• The precise positioning of the cells is decided.
Semi Custom Design
Flow
• Routing :
• The interconnection between the cells and
blocks are wired.
• Extraction :
• A model of the chip is generated from the
actual physical layout ,Including the precise
device sizes,devise parasitics, and the
capacitance and resistance of the wires.
Semi Custom Design
Flow
• Postlayout simulation and verification :
• The functionality and performance of the chip
is verified in the presence of the layout
parasitics.
• If the design is found to be lacking ,iteration
on the floorplaning,placement and routing
might be necessary. Very often,this might not
solve the problem, and another round of the
sructural design phase might be necessary.
Semi Custom Design
Flow
• Tape out :
• Once the design is found to be meeting all
design goals and functions ,a binary file is
generated containing all the information
needed for mask generation.
• This file is then sent out to the ASIC vendor
or foundry. This important moment in the
life of chip is called tape out.
Semi custom
Array Based Implementation
Approaches
• It is a regular structure Approach.
• It is also called Programmable logic Array(PLA)
• This Approach is adopted by major up design
companies such as Intel,DEC.
• Advantage:
• Lower NRE
• Disadvantage:
• Lower performance ,lower integration
density,higher power dissipation.
Array Based Implementation
Approaches
• Two types of approaches :
• Prediffuced (or mask-programmable)
Arrays
• Prewired Arrays
Prediffuced Array based
Approach
• In this approach, batches of wafers containing
arrays of primitive cell or transistor are
manufactured and stored.
• All the fabrication steps needed to make
transistor are standrdized and executed without
regard to the final application.
• To transform these uncommitted into actual
design,only the desired interconnections have to
be added,determining the overall function of the
chip with only few metallization steps.
• These layer can be designed and applied to
premanufactured wafers much more
rapidly,reducing the turn around time to a week
or less.
Prediffuced Array based
Approach
• This approach is also called gate
array or sea of gate approach,
depending on the style of the
prediffused.
• Two type of gate array approach
• (1) channelled gate array approach
• (2)channelless gate array
approach(sea of gate approach)
Comparison between the
channeled (GA) vs. the
channelless (SOG) approaches
channelled gate array
approach
• channelled gate array approach places the cells in rows separated
by wiring channels.
• In channelless gate array approach routing channels can be
eliminated and routing can be performed on the top of the primitive
cells with metallization layer(occasionally leaving a cell unused ).
• SOG Advantage :
• Increased density and make it possible to achieve integration lelels
of millions of gates on single die.
• It costomizes the contact layer between metal-1 and diffusion
and/or polysilicon.so it further reduce cell size.
• Utilization factors in SOG structures are a strong function of the type
of application being implemented
• UF can be obtained 100 % for regular structure memory
• UF can be substantialy lower(75 %),due largely to wiring
restrictions.
THANK YOU

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