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Flip-Flops

Basic concepts
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Flip-Flops
A flip-flop is a bi-stable device: a circuit
having 2 stable conditions (0 or 1)
3 classes of flip-flops
latches: outputs respond immediately while
enabled (no timing control)
pulse-triggered flip-flops: outputs response
to the triggering pulse
edge-triggered flip-flops: outputs
responses to the control input edge
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Conventions
The circuit is set means output = 1
The circuit is reset means output = 0
Flip-flops have two output Q and Q or (Q and
Q)
Due to time related characteristic of the flip-
flop, Q and Q (or Q) are usually represented
as followed:
Q
t
or Q: present state
Q
t+1
or Q
+
: next state
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4 Types of Flip-Flops
SR flip-flop JK flip-flop






D flip-flop T flip-flop
S R Q
t+1
Q
t+1
0 0 Q
t
Q
t
0 1 0 1
1 0 1 0
1 1 Prohibited
J K Q
t+1
Q
t+1
0 0 Q
t
Q
t
0 1 0 1
1 0 1 0
1 1 Q
t
Q
t


D Q
t+1
Q
t+1
0 0

1

1 1 0


T Q
t+1
Q
t+1
0 Q
t
Q
t
1 Q
t
Q
t


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SR Latch
An SR (or set-reset) latch consists of
S (set) input: set the circuit
R (reset) input: reset the circuit
Q and Q output: output of the SR latch in normal and
complement form



Application example: a switch debouncer
S R Q
t+1
Q
t+1
0 0 Q
t
Q
t
0 1 0 1
1 0 1 0
1 1 Prohibited
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SR latch
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An application of the SR latch
(a) Effects of contact
bounce.



(b) A switch
debouncer.

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latch

SR
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Gated SR latch
(c)
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Gated D latch
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Timing Consideration
When using a real flip-flop, the following information
is needed to be considered:
propagation delay (t
pLH
, t
pHL
) - time needed for an
input signal to produce an output signal
minimum pulse width (t
w(min)
) - minimum amount of
time a signal must be applied
setup and hold time (t
su
, t
h
) - minimum time the
input signal must be held fixed before and after
the latching action
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Propagation delays in an SR latch
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Timing diagram for an SR latch
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Minimum pulse width constraint
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Timing diagram for a gated D latch
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Unpredictable response in a gated D latch
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Master-slave SR flip-flop
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Timing diagram for a master-slave SR flip-flop
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Master-slave J K flip-flop
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Timing diagram for master-slave J K flip-flop
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Master-slave D flip-flop
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Master-slave T flip-flop
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Positive-edge-triggered D flip-flop
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Timing diagram for a positive-edge-triggered D flip-flop
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Negative-edge-triggered D flip-flop
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Asynchronous Inputs
do not require the presence of a control
signal
preset (PR) - set the flip-flop
clear (CLR) - reset the flip-flop
useful to bring a flip-flop to a desired
initial state
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Positive-edge-triggered D flip-flop with asynchronous inputs
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Positive-edge-triggered J K flip-flop
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Positive-edge-triggered T flip-flop
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Master-slave J K flip-flop with data lockout
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Characteristic Equations
algebraic descriptions of the next-state
table of a flip-flop
constructing from the Karnaugh map for
Q
t+1
in terms of the present state and
input
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Characteristic equations