4-1

4446 Design of Microprocessor-Based Systems

Hardware Detail of Intel 8088
Dr. Esam Al_Qaralleh
CE Department
Princess Sumaya University for Technology

4-2
8088 Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
GND
A14
A13
A12
A11
A10
A9
A8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
VCC
A15
A16 / S3
A17 / S4
A18 / S5
A19 / S6
SS
0
(High)
MN / MX
RD
HOLD (RQ / GT
0
)
HLDA (RQ / GT
1
)
WR (LOCK)
IO / M
(S
2
)
DT / R (S
1
)
DEN
(S
0
)
ALE
(QS
0
)
INTA (QS
1
)
TEST
READY
RESET
10.3 CPU pin descriptions
GND
A14
A13
A12
A11
A10
A9
A8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
Vcc
A15
A16/S3
A17/S4
A18/S5
A19/S6
___
SS0 (HIGH)
___
MN/MX
___
RD
___ ____
HOLD (RQ/GT0)
___ ____
HLDA (RQ/GT1)
___ ______
WR (LOCK)
__ __
IO/M (S2)
__ __
DT/R (S1)
____ __
DEN (S0)
ALE (QS0)
_____
INTA (QS1)
_____
TEST
READY
RESET

1 40








8088









20 21
Minmode operation
signals (MN/MX=1)
Maxmode operation
signals (MN/MX=0)
Address Bus
(outputs)
Time-multiplexed
Address (outputs)/
Data Bus
(bidirectional)
Hardware
interrupt requests
(inputs)
2...5MHz,
1/3 duty cycle
(input)
0V=0,
reference
for all
voltages
5V10%
Time-
multiplexed
Address Bus
/Status signals
(outputs)
Status
signals
(outputs)
Operation Mode,
(input):
1 = minmode
(8088 generates all
the needed control
signals for a small
system),

0 = maxmode
(8288 Bus
Controller expands
the status signals to
generate more
control signals)
Interrupt
acknowledge
(output)
Control
Bus
(in,out)
4-4
8088 Pin Description
GND: 1 & 20 Both need to be connected to ground
VCC: 21 VCC = 5V
CLK: 19 Input 33% duty cycle
1/3*T 2/3*T
MN/MX: 33 Input High Minimum mode
Low Maximum mode
RESET: 21 Input Reset 8088
Duration of logic high must be greater
than 4*T
After reset, 8088 fetches instructions
starting from memory address FFFF0H
Pin Name Pin Number Direction Description
4-5
8088 Pin Description
Pin Name Pin Number Direction Description
READY 22 Input Informs the processor that the selected memory
or I/O device is ready for a data transfer
8088 Selected memory
or I/O device
Data bus
READY READY
wait for
memory
or I/O ready
Start data transfer
4-6
8088 Pin Description
Pin Name Pin Number Direction Description
HOLD 31 Input The execution of the processor is suspended
as long as HOLD is high
HLDA 30 Output Acknowledges that the processor is suspended
8088
Memory
HOLD
HLDA
Device 2
Bus
Procedure for Device 2 to use bus
Drive the HOLD signal of 8088 high
Wait for the HLDA signal of 8088
becoming high
Now, Device2 can send data to bus
4-7
8088 Pin Description
Pin Name Pin Number Direction Description
NMI 17 Input Causes a non-maskable type-2 interrupt
INTR 18 Input Indicates a maskable interrupt request
INTA 24 Output
Indicates that the processor has received an
INTR request and is beginning interrupt
processing
NMI (non-maskable interrupt): a rising edge on NMI causes a type-2 interrupt
INTR: logic high on INTR poses an interrupt request. However, this request can
be masked by IF (Interrupt enable Flag). The type of interrupt caused by
INTR is read from data bus
8088
External
device
Data bus
INTR
INTA
INTR
INTA
Data Bus Int. type
INTA: control when the interrupt type should be loaded onto the data bus
4-8
8088 Pin Description
Pin Name Pin Number Direction Description
ALE 25 Output Indicates the current data on 8088 address/data
bus are address
D Q
G
8088
A[19:8]
ALE
AD[7:0]
D[7:0]
A[7:0]
A[19:8]
D latches
Buffer
4-9
8088 Pin Description
Pin Name Pin Number Direction Description
DEN 26 Output
Disconnects data bus connection
DT / R 27 Output
Indicates the direction of data transfer
8088
AD[7:0]
Data
bus
D[7:0]
DEN
DT/R
DEN DT/ R
DEN DT/R

1 X Disconnected
0 0 To 8088
0 1 From 8088
4-10
8088 Pin Description
Pin Name Pin Number Direction Description
WR 29 Output
Indicates that the processor is writing to memory
or I/O devices
RD 32 Output
IO/ M 28 Output
Indicates that the processor is reading from
memory or I/O devices
Indicates that the processor is accessing whether
memory (IO/M=0) or I/O devices (IO/M=1)
WR
RD
IO/M
8088
Memory
WE
OE
CS
Addr.
Dec.
Addr.
Dec.
IO/M
WR or
RD
I/O
4-11
8088 Pin Description
Pin Name Pin Number Direction Description
AD[7:0] 9-16 I/O
Address / Data bus
A[19:8] 2-8, 35-39 Input
Address bus
SS
0
34 Output
TEST 23 Input
Status Output
It is examined by processor testing instructions
LOCK 29 Input
Lock output is used to lock peripherals off
the system. Activated by using the LOCK:
prefix on any instruction.
QS1 and QS0 24, 25 Input The queue status bits show status of
internal instruction queue. Provided for
access by the numeric coprocessor (8087).
10.3 CPU pin descriptions
S2 S1 S0 Indicated Operation
0 0 0 Interrupt acknowledge
0 0 1 I/O read
0 1 0 I/O write
0 1 1 Halt
1 0 0 Code access
1 0 1 Memory read
1 1 0 Memory write
1 1 1 Passive
8088 Status Signals
Interrupt Triggered on:
Disabled
via
Software Priority
NMI Rising edge No High
INT High level Yes Low
Comparison of NMI and INTR
Signal Input Output Tri-State Minmode Maxmode
CLK * * *
MN/MX * * *
S0,S1,S2 * * *
RESET * * *
READY * * *
HOLD * *
HLDA * *
NMI * * *
INTR * * *
INTA * *
RQ/GT0 * * *
RQ/GT1 * * *
LOCK * * *
ALE * *
DEN * * *
DT/R * * *
WR * * *
RD * * * *
IO/M * * *
AD0-AD7 * * * * *
A8-A19 * * * *
8088 Signal Summary
IOWR
IORD
MEMWR
MEMRD
RD
WR
IO/M
Decoding 8088 memory and I/O read/write signals
4-14
8284 Clock Generator
510
510
100K
10uF
+5V
Ready1
Ready2
RES
RDY1
RDY2
X1
X2
Ready
CLK
RESET
RESET
CLK
Ready
8284
8088
Generates 33% duty cycle clock signal
Generates RESET signal
Synchronizes ready signals from memory
and I/O devices
Basic functions:
Clock generation.
RESET synchronization.
READY synchronization.
Peripheral clock signal.
10.4 The 8284 Clock Generator
RDY1
RDY2
EFI CLK
F/C
CSYNC
AEN1
AEN2 8284
ASYNC
X1 READY
X2 RES RESET
5V
READY1
READY2
5V
10MHz
4K7
2X510
5V
10F
100K
1N4148


CLK


8088


READY
RESET
t
RES
[V]
t
RESET
1L
0L
0 = crystal oscillator
1 = TTL clock on EFI,
synchronized on CSYNC
t
X1,2
[V]
qualifiers for
READY1,-2
1 = one WAIT state
forced by READY 0 = forces the P
to froze the
current bus cycle
inserting WAIT
STATES (all
signals keep their
values), allowing
slower devices
time to properly
answer.
CLK
1/3 f
osc
1/3 duty cycle
4-16
8288 Bus Controller
Separate signals are used for I/O ( IORC and IOWC ) and memory ( MRDC and MWTC ).

Also provided are advanced memory ( AIOWC ) and I/O ( AIOWC ) write strobes plus INTA .
DEN DT/R MRDC
ALE MWTC
S0 IORC
S1 8288 IOWC
S2 INTA
AMWC
AIOWC
IOB AEN CEN
10.5 The 8288 Bus Controller
8286


OE T
8282


STB OE
D Q
LE
CPU Address Bus
(A16-A19,
if needed,
should be
latched the
same way like
AD0-AD7)
CPU Data Bus
A8-A15




AD0-AD7


8088






S0
S1
S2
Memory ReaD Command
Memory WriTe Command
Input/Output Read Command
Input/Output Write Command
INTerrupt Acknowledge
Advanced Memory Write Command
Advanced Input/Output Write Command
Status Signals
(codify the bus
cycle type)
Control
Bus
Max one active at a time,
identifying Memory vs. I/O
and Read vs. Write
Identify the Memory Byte
(one of 2
20
(2
16
in example))
OR the I/O port (one of 2
16
)
to be read OR write
in the current bus cycle
Advanced Write Commands,
providing additional access time
for the selected circuit
Data to be transferred
in the current bus cycle
Data Transmit/Receive
5V
CLK
Address
Latch
Enable
Data Enable
Command Enable
Address Enable I/O Bus only
74LS244


G1 G2
4-18
System Timing Diagrams
T-State:
One clock period is referred to as a T-State
T-State
An operation takes an integer number of T-States
CPU Bus Cycle:
A bus cycle consists of 4 or more T-States
T1 T2 T3 T4
4-19
Dump address on address bus.
Issue a read ( RD ) and set M/ IO to 1.
Wait for memory access cycle.

Memory Read Timing Diagrams
4-20
Memory Read Timing Diagrams
T1 T2
T3 T4
CLK
ALE
A[19:16] A[19:16] S3-S6
A[15:8] A[15:8]
AD[7:0] A[7:0] D[7:0]
IO/M
DT/R
DEN
RD
WR
A[15:8]
AD[7:0]
A[15:0]
Buffer
D latch
Trans
-ceiver
D[7:0]
DT/R
DEN
IO/M
WR
RD
8088
Memory
4-21
Dump address on address bus.
Dump data on data bus.
Issue a write ( WR ) and set M/ IO to 1.
Memory Write Timing Diagrams
4-22
Memory Write Timing Diagrams
T1 T2
T3 T4
CLK
ALE
A[19:16] A[19:16] S3-S6
A[15:8] A[15:8]
AD[7:0] A[7:0] D[7:0]
IO/M
DT/R
DEN
RD
WR
A[15:8]
AD[7:0]
A[15:0]
Buffer
D latch
Trans
-ceiver
D[7:0]
DT/R
DEN
IO/M
WR
RD
8088
Memory
4-23
Bus Timing
During T 1 :
The address is placed on the Address/Data bus.
Control signals M/ IO , ALE and DT/ R specify memory or I/O, latch the
address onto the address bus and set the direction of data transfer on data bus.
During T 2 :
8086 issues the RD or WR signal, DEN , and, for a write, the data.
DEN enables the memory or I/O device to receive the data for writes and the 8086 to
receive the data for reads.
During T 3 :
This cycle is provided to allow memory to access data.
READY is sampled at the end of T 2 .
If low, T 3 becomes a wait state.
Otherwise, the data bus is sampled at the end of T 3 .
During T 4 :
All bus signals are deactivated, in preparation for next bus cycle.
Data is sampled for reads, writes occur for writes.
4-24
Setup & Hold Time
Setup time The time before the rising edge of the clock, while the data must
be valid and constant
Hold time The time after the rising edge of the clock during which the data
must remain valid and constant
4-25
Bus Timing Diagram
4-26
Bus Timing
Timing:
Each BUS CYCLE on the 8086 equals four system clocking periods (T states).
The clock rate is 5MHz , therefore one Bus Cycle is 800ns .
The transfer rate is 1.25MHz .

Memory specs (memory access time) must match constraints of system timing.

For example, bus timing for a read operation shows almost 600ns are needed to
read data.
However, memory must access faster due to setup times, e.g. Address setup and data
setup.
This subtracts off about 150ns .
Therefore, memory must access in at least 450ns minus another 30-40ns guard band for
buffers and decoders.
420ns DRAM required for the 8086.

4-27
10.6 System Time Diagrams - CPU Bus Cycle
T
2
T
3
T
W
T
4

Read Cycle
(instruction fetch and memory operand read)
A
8
- A
15
Address latches store the actual values
Memory Cycle (I/O cycle is similar but IO/M = 1)
S
3
- S
6
Tri-state
A
16
-A
19
A
0
- A
7
T
1

CLK
ALE
IO/M
A
16
- A
19
A
8
- A
15
RD
AD
0
- AD
7
DT/R
READY
DEN
Direction READ for the Data Buffer
Enables Data Buffer
WR
AD
0
- AD
7
DT/R
Write Cycle (memory operand write)
A
0
- A
7
D
0
- D
7
(Data out)

DEN
Direction READ for the Data Buffer
Enables Data Buffer
Memory reads Data Bus
The slow device drives READY= 0
the P samples READY
(if 0 a WAIT state follows)
D
0
- D
7
(Data in)

P reads Data Bus
4-29
Interrupt Acknowledge Timing Diagrams
T1 T2
T3 T4


CLK
INTR
INTA
D[7:0]
8088
External
device
Data bus
INTR
INTA
It takes one bus cycle to perform an interrupt acknowledge
During T1, the process tri-states the address bus
During T2, INTA is pulled low and remains low until it becomes inactive in T4
The interrupting devices places an 8-bit interrupt type during INTA is active
Int. Type
4-30
HOLD/HLDA Timing Diagrams
T2 T3 T4


CLK
HOLD
8088
Memory
HOLD
HLDA
Device 2
Bus
HLDA
Hold State
The processor will examine HOLD signal at every rising clock edge

If HOLD=1, the processor will pull HLDA high at the end of T4 state (end of
the execution of the current instruction) and suspend its normal operation

If HOLD=0, the processor will pull down HLDA at the falling clock edge
and resume its normal operation
10.6 System Time Diagrams - INT and HOLD
T
4
T
1

HOLD/HLDA Timing
CLK
HOLD
HLDA

HOLD state: the P releases the Address,
Data, Control and Status buses (these pins
are tri-sated (high impedance)
only after ending the current bus cycle
CLK
INTA
AD
0
- AD
7
T
2
T
3
T
4
T
1

INT type

Tri-state
Minmode Interrupt acknowledge timing
a single INTA cycle in minmode.
CLK
LOCK
INTA
AD
0
- AD
7
T
2
T
3
T
4
T
1
T
2
T
3
T
4
T
1

INT type

First INTA cycle Second INTA cycle
Tri-state
Maxmode Interrupt acknowledge timing
two INTA cycles in maxmode, the device
requesting INT has to drive the INT type
on the Data Bus, during the second cycle.
Prevents P to enter a HOLD state
10.7 Personal Computer Bus Standards
CPU
Memory Bus
Cash
Memory
Memory
Controller
P Bus
Main
Memory
I/O Bus
Controller
Plug-in I/O
Boards
I/O Bus
Motherboard
I/O Circuits
CPU
Memory
I/O
P Bus
CPU
Cash
Memory
P Bus
Memory Bus
Memory
Controller
Main
Memory
Bridge
Controller
Motherboard- and Fast
Plug-in I/O Circuits
PCI Bus
I/O Bus
Controller
I/O Bus
Slow Plug-in
I/O Boards
Simple P System
Architecture
PCI (Peripheral Component Interconnect bus)
based Architecture
Medium Complexity PC Architecture
- ISA = Industry Standard
Architecture (8 data bits =
PC-XT bus, or 16 data bits
= PC-AT bus)
- EISA = Extended ISA
- MCA = Micro Channel
Architecture (only IBM)
4-33
Dual Independent Bus (DIB)
Backside Bus
Frontside Bus
4-34
Different level of Busses