A DSTATCOM TOPOLOGY WITH

REDUCED DC-LINK VOLTAGE RATING

FOR LOAD COMPENSATION WITH
NONSTIFF SOURCE


PRESENTED BY
P.SWARNALATHA(13T81D4314)
M.TECH( PE)


Contents:
Introduction
Circuit diagram
Working procedure
D-STATCOM
Distribution system
Applications
Advantages
conclusion
Introduction:
The proposed topology enables DSTATCOM to have a
reduced dc-link voltage without compromising the com-
pensation capability.
It uses a series capacitor along with the inter-facing
inductor and a shunt filter capacitor.
Circuit diagram:

Working Procedure:
THE topology consists of 2 capacitors one is n series with
the interfacing inductor of the active filter and the other is
in shunt with the active filter .
The series capacitor enables reduction in dc-link voltage
while simultaneously compensating the reactive power
required by the load so as to maintain unity power factor
without compromising DSTATCOM performance.
The simulation studies are carried out using a PSCAD
simulator .

Design of VSI parameters:

Cdc=((2x-x/2)nT)/(( 1.8Vm)- ( 1 . 4 v m ) )
Lf=1.6Vm/4hfswmax
Z=R+JXL .
In addition, D-STATCOM is also capable to generate or
absorbs reactive power. If the output voltage of the VSC is
greater than AC bus terminal voltages, D-STATCOM is
said to be in capacitive mode. So, it will compensate the
reactive power through AC system and regulates missing
voltages.
These voltages are in phase and coupled with the AC
system through the reactance of coupling transformers.

Suitable adjustment of the phase and magnitude of the
DSTATCOM output voltages allows effectives control of
active and reactive power exchanges between D-
STATCOM and AC system.
Which states that the dc-link voltage should be greater
than or equal to root 6 times the phase voltage of the
system for distortion-free compensation
DESIGN OF SHUNT CAPACITOR
CSH

In the presence of the feeder impedance, i.e.,
nonstiff source in the system, the terminal voltages are
distorted due to un-balance and nonlinear load
currents. In order to improve the performance,
positive sequence voltages at the terminal are
extracted using the power-invariant instantaneous
symmetrical transformation and are used for
generating the reference currents

DESIGN OF SERIES CAPACITOR C
F

The fundamental filter current drawn by the shunt filter
capacitor is neglected while designing the series capacitor
value. This is because the impedance between the PCC and
ground becomes very high when C
sh
is chosen much
smaller than C
sho
at fundamental frequency, and thus, the
fundamental current drawn by the shunt capacitor is
negligible. The design of the C
f
depends upon the value to
which the dc-link voltage is reduced.
Advantages
Compensating the load at a lower dc-link voltage under
nonstiff source.
Reduces harmonic distortion
Improves power factor.less average switchng frequency
Applications
Power quality improvement in distribution networks.
To mitigate the voltage sags
Conclusion:
The proposed method is validated through simulation and
experimental studies in a 3- distribution system with the
neutral clamped DSTATCOM topology. which has the
capability of compensating the load at a lower dc-link
voltage under nonstiff source. The proposed topology has
less average switching frequency, less THDs in the source
currents and terminal voltages with reduced dc-link
voltage as compared to the conventional DSTATCOM
topology.

THANK YOU