8-8-2006 MOS Circuit Design

Lecture-2@2006
FABRICATION OF MOSFET

Dr. Arti Noor,
M. Tech Division, CDAC Noida.
Email : artinoor@cdacnoida.in


MOS Circuit Design
Lecture-2@2006

Introduction

IC technologies :

NMOS
PMOS
CMOS
SOI
BiCMOS
GaAs






MOS Circuit Design
Lecture-2@2006

Basic Fabrication Steps:


Wafer Processing.
Mask making.
Photolithography.
Oxidation.
Diffusion.
Etching.
Poly-gate formation.
Metallization.






MOS Circuit Design
Lecture-2@2006

Basic Fabrication Steps:
Wafer Processing : single crystal wafer, diameter
70 mm to 200 mm, thickness less than 1mm, front
face polished, scratch free mirror finish.












MOS Circuit Design
Lecture-2@2006

Basic Fabrication Steps:

Mask making :
After complete design the drawing is broken
into subsequent IC processing steps.
These steps are called mask levels.
Electron beam machine known as pattern
generator is used for mask making.
The interface is CIF between layout and mask
machine.
Mask machine transfers design features
directly on photosensitive glass plate using
CIF.




MOS Circuit Design
Lecture-2@2006

Basic Fabrication Steps:

Photolithography : The process used to transfer a
pattern on wafer is called lithography. The
process has 6 steps.

1. Photoresist Coating.
2. Pre baking.








MOS Circuit Design
Lecture-2@2006

Basic Fabrication Steps:

3. Alignment and exposing.













MOS Circuit Design
Lecture-2@2006

Basic Fabrication Steps:

4. Development.
5. Post baking.












MOS Circuit Design
Lecture-2@2006

Basic Fabrication Steps:

6. Etching Removal of photoresist.













MOS Circuit Design
Lecture-2@2006

Basic Fabrication Steps:

Wafer after Removal of photoresist.













MOS Circuit Design
Lecture-2@2006

Basic Fabrication Steps:

Oxidation : The purpose of SiO
2
layer is


1. acts as component in MOS.
2. acts as mask against diffusion.
3. used to isolate the devices
4. provides electrical isolation in multilevel
metallization.

Several techniques : thermal oxidation, wet
oxidation, CVD, Plasma oxidation.

LOCOS Oxidation for isolation.




MOS Circuit Design
Lecture-2@2006

Basic Fabrication Steps:

Diffusion : The purpose is to alter the type of
conductivity by diffusing impurities.


Goal :
1. Control of impurity concentration.
2. Uniformity.
3. Reproducibility.

Two techniques : Furnace diffusion and Ion
Implantation.




MOS Circuit Design
Lecture-2@2006

Basic Fabrication Steps:

Ion Implantation : has the capability of highly
prcised control of number of implanted dopant
atoms. Concentration range from 10
14
to 10
21

atoms/ cm
3
.


Mainly used for:

Source and drain.
Threshold adjustment.
Reduction of punch through effects.




MOS Circuit Design
Lecture-2@2006

Basic Fabrication Steps:

Poly gate : poly silicon is used as a gate. Common
method is CVD.


For poly gate
SiH
4
(g) + heat Si(s) + 2H
2
; T= 600 to 700
o
c in N
2
Presence.

For SiO
2
SiH
4
+ 2O
2
SiO
2
+ 2H
2
O; T= 400 to 500
o
c in N
2
Presence.

For Silicon Nitride
3SiH
4
+ 4NH
3
Si
3
N
4
+ 12H
2
; T= 800 to 900
o
c in N
2
Presence.

This is used as dielectric film. This stops Sodium
contamination.



MOS Circuit Design
Lecture-2@2006

Basic Fabrication Steps:

Metallization :

Is done to provide low resistance
interconnects.

Common method is evaporation and
sputtering.

In high vacuum chamber the metal is deposited
by evaporation with subsequent condensation
on substrate target.




MOS Circuit Design
Lecture-2@2006

Basic NMOS Fabrication Steps:

Formation of SiO
2
and then photoresist coating














MOS Circuit Design
Lecture-2@2006

Basic NMOS Fabrication Steps:

Photo-mask and then etching of selected area.














MOS Circuit Design
Lecture-2@2006

Basic NMOS Fabrication Steps:















The wafer is then placed into an oxidation furnace
and thin oxide (the gate oxide) is grown to cover the
etched region
MOS Circuit Design
Lecture-2@2006

Basic NMOS Fabrication Steps:
A layer of poly-crystalline silicon is deposited all
over the wafer.
This layer is then patterned and etched to form the
gate of transistor.









MOS Circuit Design
Lecture-2@2006

Basic NMOS Fabrication Steps:

An n-type dopant is introduced into the opened
regions and diffused into the wafers.










MOS Circuit Design
Lecture-2@2006

Basic NMOS Fabrication Steps:













Oxide is deposited using Low Pressure Chemical Vapor
Deposition (LPCVD) and is used for top coat protection.

MOS Circuit Design
Lecture-2@2006

Basic NMOS Fabrication Steps:













A layer of aluminum is deposited all over the wafer
and patterned and etched to form the
interconnecting layers and the connections to
channel Metal Oxide Semiconductor.
MOS Circuit Design
Lecture-2@2006

N-Well CMOS Fabrication Steps















MOS Circuit Design
Lecture-2@2006

N-Well CMOS Fabrication Steps (contd.)















MOS Circuit Design
Lecture-2@2006

N-Well CMOS Fabrication Steps (contd.)















MOS Circuit Design
Lecture-2@2006














MOS Circuit Design
Lecture-2@2006
CMOS Inverter in twin tub process














MOS Circuit Design
Lecture-2@2006
CMOS DESIGN RULES

Fabrication processes are pattern independent.

Design Rules are constraints poses by
processing line in the form of minimum
allowable values for width, separation, extension
and overlap.

The complexity of design rules depends upon
how well a process is characterized.




MOS Circuit Design
Lecture-2@2006
CMOS DESIGN RULES (con.)

A proper set of design rules must take into
account the following considerations:

Characteristic of Photolithography.

Etching capabilities.

Expected misalignment Variance.

Electrical Constraints.


MOS Circuit Design
Lecture-2@2006

Photolithography Constraints:


Minimum geometry to be resolved in the
photoresist.

Impose condition on minimum line width
and separation.

Width and spacing rules must be relaxed
to the upper most non-uniform layer.

MOS Circuit Design
Lecture-2@2006
PHOTOLITHOGRAPHY
MOS Circuit Design
Lecture-2@2006
Etching Constraints:

Additional constraints on line width.

Contact cut dimensions are critical.

Rules are made to etch minimum size.

MOS Circuit Design
Lecture-2@2006
Misalignment Variance:

All subsequent layers are aligned with
previous layer

Proper choice of alignment sequence plays
important role.

Electrical Constraints:

No physical contact in adjacent lines.
Minimum line width must be wide
enough to avoid electromigration.

MOS Circuit Design
Lecture-2@2006
Three approaches for Design Rules


Micron based.



based.







MOS Circuit Design
Lecture-2@2006
CMOS N-Well Design Rules














MOS Circuit Design
Lecture-2@2006
CMOS N-Well Design Rules














MOS Circuit Design
Lecture-2@2006
CMOS N-Well Design Rules














MOS Circuit Design
Lecture-2@2006
CMOS N-Well Design Rules














MOS Circuit Design
Lecture-2@2006
CMOS N-Well Design Rules














MOS Circuit Design
Lecture-2@2006
CMOS N-Well Design Rules














MOS Circuit Design
Lecture-2@2006
CMOS N-Well Design Rules














MOS Circuit Design
Lecture-2@2006
Assignment-1



Draw N-MOSFET which has length 5m and width
10m on Graph Sheet.

Submit your assignment on next class.







MOS Circuit Design
Lecture-2@2006
Next Class Topic



MOS Transistor