Microprocessor and Microcontroller

Chapter 1
Intel 8086/8088
Microprocessor family
Prepared by : Bhushan Inje
Computer Engineering Department
Learning Objectives
Introduction :-
Features of Intel 8086/8088.
Architecture and Programmers Model of 8086/8088.
Register organization.
Signal description.
Memory organization.
Bus operations.
I/O addressing capability.
Minimum and maximum modes of 8086 processor.

We also study the details of 8088 processor.

Intel 8086/8088 Microprocessor Family
Introduction :-
In 1978, Intel came out with the 8086 processor.
The Intel 8086 is a 16-bit microprocessor.
Implemented in N-channel, silicon gate technology
(HMOS).
Packaged it in a 40-pin dual in line package.



Microprocessor
Microprocessor is a register based, multipurpose,
programmable Clock driven Electronic semiconductor
device.
It accepts Instructions from user through storage
memory; processes the data as per the given instruction
and gives the desired output.
Fig: Intel 8086 Microprocessor
Basic Computer Organization
Processor
Memory
Address Bus
Data Bus
Control Bus
Basic Computer Organization
Buses :-
All of the basic components of the computer are tied together by
communications paths called buses.
A computer bus is simply a parallel collection of conductors that carry data
and control signals from one unit to another.
Buses having following Types
Address Bus :-
It is unidirectional bus
It carries addresses generated by the microprocessor to the memory and I/O
elements of the computer.
Data Bus:-
The data bus is bi-directional in nature.
The direction for data movement is the same for Read and Write operations
between the microprocessor and Input/output devices.
Control Bus:-
The control bus carries the timing and control signals necessary to coordinate the
activities of the entire system.




Features of 8086 microprocessors
The 8086 is a 16-bit microprocessor.
The 8086 has a 16-bit data bus.(Read and Write)
The 8086 has a 20-bit address bus. can access up to 2
20
memory locations ( 1 MB) .
The 8086 can generate 16-bit I/O address.
It can support up to 64K I/O ports.
The 8086 provides fourteen 16-bit registers.
The 8086 has multiplexed address and data bus.
It requires +5V power supply.
The Intel 8086 supports multiprogramming.
The 8086 provides powerful instruction set and the
addressing modes.

Internal Architecture of 8086
Architecture of 8086
It is divided in two groups to speeds up processing
Bus Interface Unit : It performs all bus operations and
communicates with external world.
The BIU sends out addresses, fetches instructions from
memory, reads data from ports and memory. and writes data
to ports and memory.
Instruction Queue
Segment Register
Instruction Pointer
Execution Unit : It executes the instructions made available
from Queue. Main blocks
Flag Register (flip-flop)
Register Group
ALU
Control Circuitry
Architecture of 8086 (Cont)
8086 Programmers Model
Register Organization :-
Fig . Register Organization of 8086
8086 Programmers Model
ES
CS
SS
DS
IP
AH
BH
CH
DH
AL
BL
CL
DL
SP
BP
SI
DI
FLAGS
AX
BX
CX
DX
Extra Segment
Code Segment
Stack Segment
Data Segment
Instruction Pointer
Accumulator
Base Register
Count Register
Data Register
Stack Pointer
Base Pointer
Source Index Register
Destination Index Register
BIU registers
(20 bit adder)
EU registers
16 bit arithmetic
General Purpose Registers
The general purpose registers are either used for
holding data, variables and intermediate results
temporarily.
They can also be used as a counters or used for storing
offset address for some particular addressing modes.
The register AX is used as 16-bit accumulator whereas
register AL (lower byte of AX) is used as 8-bit
accumulator.
AX AH-AL
BX BH-BL
CX CH-CL
DX DH-DL
AH AL
16-bit
8-bit 8-bit
Architecture of 8086 (Cont)
Flag Registers :-

Conditional Flags
Control Flags
Architecture of 8086 (Cont)
Flag Registers :-
Flag is flip-flop or Latches. (SR,D,T,JK)
Flag register in EU is of 16-bit and is shown in fig.
Flags Register determines the current state of the
processor.
They are modified automatically by CPU after
mathematical operations.
This allows to determine the type of the result, and to
determine conditions to transfer control to other parts of
the program.
8086 has 9 flags and they are divided into two categories:
1. Conditional Flags
2. Control Flags




Flag Registers Cont.
Conditional Flags :-
Conditional flags represent result of last arithmetic or logical
instruction executed. Conditional flags are as follows:
Carry Flag (CF): This flag indicates an overflow condition for unsigned
integer arithmetic.
Auxiliary Flag (AF):
If an operation performed in ALU generates a carry/barrow from lower nibble
(i.e. D0 D3) to upper nibble (i.e. D4 D7), the AF flag is set i.e. carry given by
D3 bit to D4 is AF flag.
This is not a general-purpose flag,
It is used internally by the processor to perform Binary to BCD conversion.
Parity Flag (PF):
This flag is used to indicate the parity of result.
If lower order 8-bits of the result contains even number of 1s, the Parity Flag is
set and for odd number of 1s, the Parity Flag is reset.
Zero Flag (ZF): It is set if the result of arithmetic or logical operation is
zero else it is reset.
Sign Flag (SF): In sign magnitude format the sign of number is indicated
by MSB bit. If the result of operation is negative, sign flag is set.
Flag Registers Cont.
Overflow Flag (OF): It occurs when signed numbers are added or subtracted. An
of indicates that the result has exceeded the capacity of machine
Control Flags :- Control flags are set or reset with intent to control the
operations of the execution unit. Control flags are as follows:
1. Trap Flag (TF):
a. It is used for single step control.
b. It allows user to execute one instruction of a program at a time for
debugging.
c. When trap flag is set, program can be run in single step mode.
2. Interrupt Flag (IF):
a. It is an interrupt enable/disable flag.
b. If it is set, the maskable interrupt of 8086 is enabled and if it is reset, the
interrupt is disabled.
c. It can be set by executing instruction sit and can be cleared by executing
CLI instruction.
3. Direction Flag (DF):
a. It is used in string operation.
b. If it is set, string bytes are accessed from higher memory address to
lower memory address.
c. When it is reset, the string bytes are accessed from lower memory address
to higher memory address.
Architecture of 8086 (Cont.)
Segment Registers
Fig. Memory Segmentation and Segment Registers
Segment Registers Cont..
Segment Registers Cont
The following show the usage of segment
in memory
Segment Usage
Code (CS) Space to store program that will be executed
Data (DS) Space to store data that will be processed
Stack (SS) Special space to store information needed by
microprocessor to execute subroutine or interrupt service
Extra (ES) Function is the same as DS
Architecture of 8086 (Cont)
Pointer and Index Registers - SP, BP, SI, DI, IP
SP - Stack Pointer
Always points to top item on the stack
Offset address relative to SS
Always points to word (byte at even address)
An empty stack will had SP = FFFFh
BP - Base pointer
Primarily used to access parameters passed via the stack
Offset address relative to SS
SI - Source Index
Can be used for pointer addressing of data
Used as source in some string processing instructions
Offset address relative to DS
DI - Destination Index
Can be used for pointer addressing of data
Used as destination in some string processing instructions
Offset address relative to ES
IP - Instruction Pointer
Always points to next instruction to be executed
Offset address relative to CS

Segmented Memory (x86 Style)
CS
ES
SS
DS
Data
Segment
Stack
Segment
Extra
Segment
Code
Segment
Segment
Registers
System
Memory
Segment Registers:

Point to Base Address

Index Registers:

Contain Offset Value

Notation (Segmented Address):

CS:IP
DS:SI
ES:DI
SS:BP
SS:SP
00000h
FFFFFh
fragmentation
Physical Address Generation
* The CS register contains the upper 16-bits of the starting address of the CS
CS Register Segment Base


* BIU will automatically insert Zero for lowest FOUR bits of the segment base
address to get the 20 bit physical address for the starting of CS.
Starting Address of CS O BIU Adds this ZERO





* The IP registers contains the offset or distance from this address. The offset
here is 4214H.
IP Register
* Add the starting Address of CS (20 bits) to the offset to get the physical
address of the location containing the next code as follows:
3 4 8 A
3 4 8 A
4 2 1 4
Starting address of CS 0
Offset in the IP Register + 0
Physical Address of the =
Location containing
next code byte
3 4 8 A
1 4 4 2
8 4 B A 3
Advantages of Segmentation
1.Segments allows two processes to easily share data.
2. It allows programmer to partition their programs into modules
that operates independently of one other.
3. Allows to extend the address ability of a processor. It allows the
use of 16-bit registers to give an addressing capability of 1MB.
4. Segmentation make it possible to separate the area for Code,
Data, Stack.
5. It is possible to increase the memory size of code, data stack
segments beyond 64K bytes by allotting more than one
segments for each area.
Instruction Pointer (IP)
Register which stores instruction address to be
executed.
Each time instruction is fetch from memory to
be executed in processor, IP content will be
added so that it always show to the next
instruction.
If branch instruction, the IP content will be
loaded with new value which is the branch
address.

Architecture of 8086 (Cont)
Control Circuit
It is a part of EU.
It is used for directing the internal operations.
Decoder
The process of translation from instruction into
action is known as decoding.
A decoder in a EU is used for translating the
instruction fetched from the memory into series of
action.

Pin Diagram of 8086
40 pins of 8086 are
Supply pins (03 pins)
Clock related pins (03 pins)
Address & data pins (21 pins)
Interrupt pins (02 pins)
Other control pins (03 pins)
Mode multiplexed signals (08 pins)
[ MIN mode & MAX mode signal ]

Pin Diagram of 8086
Pin Diagram of 8086
I. Supply Pins
Three supply pins are
VCC (Pin no. 40) : Used for power supply i.e. +5v

Two separate GROUND pins (Pin no. 1 & 20 ) for heat
dissipation.
II. Clock related Pins
CLK (pin no.19): provides the basic timing for the
processor.
8086 does not have an on chip clock generator, hence
an external clock generator (8284) provides this signal.

RESET (pin no. 21): It causes the processor to immediately
terminate its present activity. The 8284 clock generator
provides this signal.
It clears all the flags registers, the instruction Queue,
the DS,ES,SS and IP registers and sets the bits of CS
registers.