Workshop Sync

Protection notice / Copyright notice
Workshop Synchronisation
Networks
Version 1.2 English / January 2007

Copyright Siemens Networks GmbH & Co KG. All rights reserved.
Page 2 January 2007

Copyright Siemens Networks GmbH & Co KG / All rights reserved
SN FN1 E AT
Workshop Synchronization Networks
A look at the
History

Page 3 January 2007

SN FN1 E AT
Synchronization Network at PDH-Age
Network
PR
C
2MHz
2MBit/s
Since PDH was fully transparent for the clock signal
the synchronization network was built by the switches.
Typical star topology with hierarchical structure.
The switches are the master in the sync. network
while the transport network virtually does not exist.
PDH Network
Page 4 January 2007

SN FN1 E AT
Synchronization Network at SDH-Age
Network
PR
C
2MHz
2MBit/s
With the invention of SDH the STM signal carries
the clock as well as the information about the
clock quality. It is not possible anymore to pass an
SDH network transparently with 2MBit/s.
The SDH network now becomes clock master and the
switches are slaves of the
SDH network.
SDH Network
Page 5 January 2007

SN FN1 E AT
Major Changes for Synchronization by SDH

TDM Switches contain still high accurate clock-devices thus they
definitely can be used instead of an SSU.

Traditional planning of clock hierarchy with TDM Switches does not
make any further sense (but it is not harmful).

Further usage of 2MBit/s Signals for synchronization of TDM Switches is
not possible any more. Without further precautions a 2MBit/s signal
which has passed an SDH network cannot be used for synchronization!

Page 6 January 2007

SN FN1 E AT
A brief look at
Standards &
Recommendations
Page 7 January 2007

SN FN1 E AT
Overview about Recommendations
G.803 Architecture of Transport Networks based on the SDH hierarchy
G.810 Definitions & Terminology for Synchronization Networks
G.811 Timing Characteristics of Primary Reference Clocks (PRC)
G.812 Requirements of Slave Clocks suitable for use as Node Clocks
in Synchronization Networks
G.822 Controlled Slip rate objectives on an International Digital Connect.
G.823 Jitter and Wander in Networks based on 2Mbit hierarchy
G.825 Jitter and Wander in Networks based on the SDH hierarchy
G.8251 The Control of Jitter and Wander within the Optical Transport
Network
G.8261 Timing and Synchronization Aspects in Packet Networks
G.703 Physical interface characteristics of hierarchical and clock signals
G.704 Frame structures for the different hierarchical levels, e.g. 2Mbit/s.
G.709 Network node interface for the Optical Transport Network (OTN)
G.783 Characteristics of SDH equipment functional blocks

Page 8 January 2007

SN FN1 E AT
CCITT / ITU Recommendations (G.803 Basics 1/2)
Telecommunications Network
Provider A
Telecommunications Network
Provider B
CCITT/ITU recommends that each
provider has to ensure a clock
quality of 10
-11
at the border of
Its Network.
Page 9 January 2007

SN FN1 E AT
Bode
Boundary
a)
a)
a)
a)
a) Timing only
Synchronization

link (s)
Distribution to other
G.813 clocks
outside the node
SDH
Network
element
clock
SDH
Network
element
clock
SDH
network
Element
clock
SDH
network
element
clock
Node Clock
Synchronization network
architecture intra-node
distribution
Page 10 January 2007

SN FN1 E AT
Slave
G.812
transit

PRC
G.811
Slave
G.812
transit
Slave
G.812
transit or
local
1st (K-1)th Kth
N SDH network element clocks
For worst-case scenario calculation purposes:
K = 10 (filtering clocks)
N = 20 with restriction that total number of
SDH network element clocks is limited to 60
Number of clocks are limited in order to ensure quality over the whole
synchronization domain.

SN FN1 E AT

Timing Marker S1 SSM Bits (G.707 / G.781 Option I)
S1 (b5..b8) SSM
(hex)

Meaning Frequency stability
(required by CCITT)
Quality
level
Frameslip
0010

2 PRC (G.811) 1*10-11 CS /
1*10-10 RB
Q1 1 in ~ 70 days
1 in ~ 7 days
0100

4 SRC transit (G.812) 1*10-9 per day Q2 1 in 17 h
1000

8 SRC local (G.812) 2*10-8 per day Q3
1011 B SETS (clock is derived)
from a SETS in holdover
or free run mode, G.81s)

4.6*10-6 Q4
1 in 2 h
0000

O Quality unknown - Q5
1111

F Dont use for sync. - Q6
- - Signal fail detected
at the port receiving an
STM-N-signal

-

SF

Information about Quality is distributed within the SDH Network by SSM Bits
A
u
t
o
m
a
t
i
c
a
l
l
y

s
e
t

u
s
u
a
l
l
y

r
e
f
u
s
e
d

|

a
c
c
e
p
t
e
d

f
o
r

s
y
n
c
.


SN FN1 E AT
Delay Times in Synchronization Networks (G.781)
Changing synchronization flow in a chain of 20 NEs requires 39 steps.

Step 1: Ref. 1 disappears from the first NE of the chain, NE 1 goes into
holdover mode and transmits a new SSM (T
HM
2 s max.)
Step 2 to 19: NE n (n = 2,3,,19) forwards the new SSM without switch of
reference (T
NSM
200 ms max.)
Step 20: NE 20 switches to Ref. 2 (T
SM
500ms max.)
Step 21 to 39: NE n (n = 19, 18,,1) changes to sync received from NR n+1
(T
SM
500ms max.)
Total time for restoration: 15,6 s (T
HM
+ 18 T
NSM
+ 20 T
SM
)
REF. 1
NE NE NE NE NE
REF. 2
1 n 20

SN FN1 E AT
Delay for Switching Back
Restoration to original source a chain of 20 NEs requires 40 steps.

Step 1: Ref. 1 Re-appears at the first NE of the chain, NE 1 waits until
wait time to restore is over (T
WTR
0 12 min in steps
of 1 min
default 5min)
Step 2: NE 1 switches to Ref. 1 (T
SM
500ms max.)
Step 3 to 40: Continuous repetition of step 1 & 2

Typical time for restoration: 20min and 10s (20*T
WTR
+ 20 T
SM
)
REF. 1
NE NE NE NE NE
REF. 2
1 n 20

SN FN1 E AT
Synchronisation
Features in
SDH Devices


SN FN1 E AT
Clock Input
Most SDH devices are able to derive synchronization four different sources:
SDH Signals (Line or Tributary)
PDH Tributary Port (2/34/140MBit/s, but not for each NE)
T3 (2MHz / 2 MBit/s input)
Internal Device Clock (Holdover)
Whether an incoming SDH signal may be used for synchronization is
decided on behalf of the timing marker.
For 2MHz at T3 there is no timing marker therefore it is the task of the
planner to define a quality level this has to be set manually. For 2MBit/s at
T3 timing marker can be used if the connected device is able to deliver it.
In addition all sources need to have a value for priority where holdover
always is set automatically as the last resort.
Today all SDH devices work by quality ahead of priority.

SN FN1 E AT
Clock Output
Every SDH device is able to forward synchronization signals to at least
three different kinds of output ports:
SDH Signals (Line or Tributary)
PDH 2MBit/s Tributary Port (if applicable)
T4 (2MHz or 2MBit/s output depends on NE types)
If SDH signals are forwarded the SDH device itself will create values of
the timing marker.
When T4 2MHz is used there is no timing marker available by nature.
In case the SDH device is not in an appropriate mode the T4 output
will be squelched. At T4 2MBit/s timing marker may be transferred.
In case a 2MBit/s Signal from live traffic shall be used for clock
output retiming is mandatory!

SN FN1 E AT
Wander on VC12 Signals & Retiming
Actions like grooming or cross connecting typically will require
shifting of single VC12 signals inside the VC4 container. These
actions cause a very slow jitter of the concerned VC12 where the
frequency is around 2MHz. This effect is called Wander.
Wander can be eliminated only by retiming!
Problems:
1. Retiming consumes computing capacity and buffer size thus the No.
of ports using retiming mode per device or per card is limited
(typically for elder devices)
2. Several different retiming modes (and there are variations from
device to device). Which one is the right one?
3. Murphy's Law: The operator will switch off exactly the one 2Mbit/s
output which used for synchronization.
Planning Rule: Avoid synchronization via 2MBit/s whenever possible!

SN FN1 E AT
Engineering Rules
for
Synchronization Networks


SN FN1 E AT
Rules for Synchronization Network Planning (1/2)
Do not over engineer & avoid clock loops under any circumstance!

Keep synchronization network as simple as possible
One primary path for main clock supply & a second path for
redundancy purposes are totally sufficient.
Consequently there is a maximum of 3 priorities in the network:
1
st
for primary, 2
nd
for redundancy, 3
rd
for holdover mode.

This is what normal human beings usually can handle in planning,
installation & line-up, as well as in maintenance & operations.

SN FN1 E AT
Rules for Synchronization Network Planning (2/2)
It can be extremely difficult to analyze every stage of a
complex network and there is a certain probability that
some things still remain over-looked.

Every complex network topology can be fragmented into
three simple, fully tested & reliable basic network models.

SN FN1 E AT
Synchronization Settings on SDH Devices
PRC
2
SDH
2
F
lock
2
1
SDH
lock
2
1
Priority per port:
Defined by planer.
Set manually
Clock quality at
the input port:
Defined by planer.
Set manually
Timing marker:
Set automatically
by SDH device
Internal clock:
May either be
locked to PRC or
may run in
holdover mode
(SETS)

SN FN1 E AT

Connecting Clocks to the Network (1/2)
N
E
PRC
2
2
1
SDH
1
2
2
Input Priority
SSMB setting manually defined value
SSMB automatically generated value
SSU
4
4
1
2
SSU Clock Refresh
(without SASE)
SDH
N
E
Standby Clock
SSU
4
2
2
2
SDH
N
E
1

SN FN1 E AT
Connecting Clocks to the Network (2/2)
SSU Clock Refresh using SASE/Bits
(2MBit/s interfaces required).
Caution: In order to avoid loops the NE
and the SSU must support SASE Bits
SSU
2
1
2
SDH
N
E
Normal operation
2 2
SSU
4
1
-
SDH
N
E
Fault condition
B or F 4
AIS

SN FN1 E AT

Network Model 1: Chain with 2 Clocks (1/3)
Normal operation: PRC is master
1
st
Step: PRC fail, first SDH NE goes to holdover
PRC
2
SDH SDH SDH SDH
4
STBY
2 2 2
F
F F
<lock <lock <lock <lock
2 2 2
1 1 1 1 2
PRC
2
SDH SDH SDH SDH
4
STBY
B 2 2
F
F F
SETS <lock <lock <lock
2 2 2
1 1 1 1 2

SN FN1 E AT
2
nd
Step: PRC fail, all SDH NE change SSM state one by one
3
rd
Step: PRC fail, NE 4 changes over to standby clock

PRC
2
SDH SDH SDH SDH
4
STBY
B B B
F
F 4
SETS <lock <lock lock>
Squelch
2 2 2
1 1 1 1 2
PRC
2
SDH SDH SDH SDH
4
STBY
B B B
F
F
SETS <lock <lock <lock
Squelch
2 2 2
1 1 1 1 2
F

SN FN1 E AT
4
nd
Step: PRC fail, NE 3 changes over to standby clock
5
th
Step: PRC fail, NE 2 and 1 changing over to standby clock

PRC
2
SDH SDH SDH SDH
4
STBY
F F F
4
4 4
lock> lock> lock> lock>
Squelch
2 2 2
1 1 1 1 2
PRC
2
SDH SDH SDH SDH
4
STBY
B B F
F
4 4
SETS lock> <lock lock>
Squelch
2 2 2
1 1 1 1 2

SN FN1 E AT

Network Model 2: Ring with 1 Clock (1/4)
Normal Operation: PRC is Master
Ring is divided by a link with
both ends on Priority 2
2
SDH SDH SDH SDH
2 2 2
F
F F
lock
>lock >lock
SDH SDH SDH SDH
2 2 2
F
F F
>lock >lock
PRC
2
>lock
F
>lock
>lock
2
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1

SN FN1 E AT

1
st
Step: Connection failed, the next SDH NE goes to Holdover
2
SDH SDH SDH SDH
B 2
F F
lock SETS >lock
SDH SDH SDH SDH
2 2 2
F
F F
>lock >lock
PRC
2
>lock
F
>lock
>lock
2
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1

SN FN1 E AT

2
nd
Step: NE 3 goes into Holdover
2
SDH SDH SDH SDH
B B
F
lock SETS <lock
SDH SDH SDH SDH
2 2 2
F
F F
<lock <lock
PRC
2
<lock
F
<lock
<lock
2
2
F
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1

SN FN1 E AT

3
rd
Step: NE 4 changes to Priority 2, NE 3 and NE 2 will follow
2
SDH SDH SDH SDH
F F
2
lock lock>
SDH SDH SDH SDH
2 2 2
F
F F
<lock <lock
PRC
2
<lock
F
<lock
2
F
2
lock> lock>
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1

SN FN1 E AT
Simple Solution for Ring with two Clocks (1/3)
2
SDH SDH SDH SDH
2 2 2
F F F
lock
<lock <lock
SDH SDH SDH SDH
2 2 2
F F F
<lock <lock
PRC
2
<lock
F
<lock
2
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
STB
Y
<lock
2
4
Shortest path Primary link
2
garland
A Ring with two clocks can be split into two lines with clocks at both ends!

SN FN1 E AT
2
SDH SDH SDH SDH
2 2 2
F F
lock
<lock <lock
SDH SDH SDH SDH
2 2 2
F F F
<lock <lock
PRC
2
<lock
F
<lock
2
2
1
2
1
2
1
2
1
1
2
1
2
1
2
1
STB
Y
<lock
2
4
garland
Two unidirectional links will guarantee that a loop can never happen!

SN FN1 E AT
4
2
SDH SDH SDH SDH
2 2 2
F F
lock
lock lock
SDH SDH SDH SDH
2 2 2
F F F
PRC
2
lock
F
lock
2
2
1
2
1
2
1
2
1
1
2
1
2
1
2
1
STB
Y
lock
2
4
garland
Minor issue: When a link is broken quality may degrade in some places.
lock lock
4
F F

SN FN1 E AT
Clock Loop in a Ring with two Clocks (1/5)
2
SDH SDH SDH SDH
2 2 2
F F
lock
lock lock
SDH SDH SDH SDH
2 2 2
F F F
lock lock
PRC
2
lock
F
lock
2
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
STB
Y
lock
3
4
A small modification in order to improve quality may already trigger a loop!

SN FN1 E AT
B
2 2 2
2 2 2
2
B
2
SDH SDH SDH SDH
B B B
F F
SETS
lock lock
SDH SDH SDH SDH
B B
F F F
lock lock
PRC
B
lock
F
lock
2
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
STB
Y
lock
3
4
Step 1: PRC fail NE 1 goes into holdover SSM switches over to B

SN FN1 E AT
F F
B
B B F F
F
4 4
F F 4 4
F F
2
SDH SDH SDH SDH
B B B
SETS
SDH SDH SDH SDH
4
PRC
F
4
F
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
STB
Y
lock
3
4
Step 2: Holdover reaches STBY clock and ring switches over
lock lock lock
lock lock
F
lock
4
2
4

SN FN1 E AT
4
F
4 4
F F F
4
2
SDH SDH SDH SDH
B
lock
SDH SDH SDH SDH
4
PRC
4
F
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
STB
Y
3
4
Step 3: NE 1 switches to quality 4 and a part of the ring will follow
lock lock lock
lock lock
F F F
F
lock
4 4
4 4
2
F F 4
4
lock

SN FN1 E AT
4 4 4
F F F F
4
2
SDH SDH SDH SDH
SDH SDH SDH SDH
4
PRC
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
STB
Y
3
4
Clock loop successfully established !
F F F F
4 4
2
4
lock
lock lock lock
lock lock lock
lock
Remark: Not the PRC itself may fail, but e.g. an access link towards PRC may do!

SN FN1 E AT
F
2
2
F
Network Model 3: Two Clocks in a Ring
2
SDH SDH SDH SDH
2 2 2
F
lock
lock lock
SDH SDH SDH SDH
2 2 2
F F F
lock lock
PRC
2
lock
F
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
STB
Y
lock
3
4
A ring split must be located in the path of the garland and there must be
a distance of at least one hop towards the STBY clock!
lock
2
Ring split with both ends on Prio 2
1

SN FN1 E AT

Generic Design Rules

1. For resiliency place two independent PRC and connect them by a
single (short) link of SDH NEs.
2. Avoid any SRC in between these both PRC
3. Subdivide all other parts of the Network either into lines or into Rings
4. Consider all lines having both ends connected to the network as
garlands to the existing network.
5. For SRC preferably use points where many of such garlands meet.
While loss of synchronization will lead to a degradation of
quality, clock loops typically cause loss of traffic.

SN FN1 E AT
A view on different
Approaches for
Synchronization
Networks

SN FN1 E AT

Master Slave (Classic Approach)
PRC
SRC
SRC
SRC
SRC
SRC
SRC
SRC
SRC
SRC
SRC
SRC
Detailed planning & implementation
necessary for the whole domain.

SN FN1 E AT

Types of Networks: PRC Islands
PRC
PRC
PRC
PRC
PRC
PRC
PRC
PRC
PRC
PRC
PRC
Simplified planning &
implementation per each island.

SN FN1 E AT

Practical Types of Networks: PRC everywhere
PRC
PRC
PRC
PRC
PRC
PRC
PRC PRC
PRC
PRC
PRC
PRC
PRC
PRC
PRC
PRC
GP
S
Planning & implementation
obsolete.
Network with accurate
phase.

SN FN1 E AT
Overview about
Configuration & Functionality
of the SSU2000e

SN FN1 E AT
Configuration of SSU2000e
Communication Section
Com module
Internal communication with all modules
User Interface via Com Ports
C
2
Com Ports
dedicated slot

SN FN1 E AT
Clock Section
1 12
1 or 2 oscillator modules of
Rubidium Stratum 2E or
Quartz Stratum 3E
dedicated slot dedicated slot

SN FN1 E AT
Input Section
3 4 5
GPS Antenna
Connectors
input ports
3 types of input modules
GPS module (only slot 3, 4)
1 port input module
3 port input module
up to 2 GPS modules possible
up to 9 input ports possible
dedicated slots for input modules

SN FN1 E AT
Output Section
6 7 8 9 10 11
Output ports
Dedicated output slots
6 output modules
3 working output modules (20 ports each 6, 8, 10)
3 redundant output modules (1:1 protection 7, 9, 11)
up to 400 more output ports with extension shelves
to extension shelf

SN FN1 E AT
Clock Quality
Measurement
by the SSU2000e


SN FN1 E AT
Clock Quality Measurement
by SSU2000e
Depending on its configuration the SSU2000e may act as a multi-
channel clock quality measuring device.
Measurement can be done individually per each input port.
Alternatively two or more input ports can be superposed.
Phase, MTIE, and TDEV can be measured against the internal RB-
Oscillator
RAW data will be stored for 24h, historic MTIE and TDEV data will be
stored for 60 days.
Access to data via ASCI Terminal or via network management.
For graphical visualization there is a module within in the Sync-Craft
Terminal Software.
Measured MTIE curve can be superposed with ETSI MTIE curves as
per G.811 or G.812.

SN FN1 E AT
Thank You!

Workshop Sync

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