Jerry Gao

June 2012
Content
What is Test?
Why Test?
Test in semiconductor manufacturing
Test Category and Test Equipment
Test-Equipments (Tester, Handler and Prober)
Tester interface with DUT
How handler or Probe interface with tester
Economics of Production Testing

What is TEST?
WHAT IS THE TEST STEPS?
CHOOSE THE TEST INSTRUMENT.
MAKE CONNECTIONS BETWEEN TEST
INSTRUMENT AND THE DEVICE
SET THE MODE OF THE INSTRUMENT
READ THE RESULT SHOWN BY THE INSTRUMENT
COMPARE READING WITH DEVICE SPECS
MAKE DECISION TO USE OR THROW AWAY DEVICE.
Why Test?
Objective: Wafer test is to verify which devices on a wafer is
functioning properly. This test is a major stage in IC
fabrication.
Objective: Final Test is of the same functional test performed
at wafer sort, except now each die is tested as a final IC
package. Final testing guarantees that the performance of
the device did not shift during the packaging process. And
the bond pads are all connected and packing process.
semiconductor manufacturing


DIP Dual Inline Package (dual indicates the package has
pins on two sides)
PDIP Plastic Dual Inline Package
PGA Pin Grid Array
BGA Ball Grid Array
SOP Small Outline Package
TSOP Thin Small Outline Package
TSSOPThin Shrink Small Outline Package (this one is really
getting small!)
SIP Single Inline Package
SIMM Single Inline Memory Modules (like the memory inside
of a computer)
QFP Quad Flat Pack (quad indicates the package has
pins on four sides)
TQFP Thin version of the QFP
MQFP Metric Quad Flat Pack
MCM Multi Chip Modules (packages with more than 1 die
Test Category:
Wafer Sort / Wafer Probe
Final Test

Test Equipment:
To separate out good or rejects dies, Wafer Sort
operation involves Tester and Probers.
To separate out good or rejects assembly samples,
Final Test operation involves Tester and Handlers.


Test Category and Test Equipment
What is Tester
Tester is an equipment with different instruments used
for testing & to measure the functionality of the IC. It
Consists of different testing equipment module such as:
Teradyne, Catalyst, etc
High-end ATE testers often consist of three major
components: a test head, a workstation. and the
mainframe.

Tester Category
Memory Tester:
EPRO 142AX, MAVERICK,
ADVANTEST T3333,T5xxx
Digital Tester:
Credence Duo, Teradyne J750, TRI (TR-6010), VTT (V7100)
Analog Tester:
Credence (ASL1K), EAGLE (ETS-200/300, ETS-88)
Spandnix (SX1300),
Mixed-Signal Tester:
Teradyne (A5XX, CATALYST), EAGLE (ETS-364)
Discreet Tester:
Juno (DTS-1000, DTS-1200, DTS2000),
Typical Tester
Main frame Test Heads
Users CPU
/Workstation
Tester in Diodes
ETS-88
ETS-200/300 ASL1K
ATE test head to DUT
ETS-88 Block Diagram
What is Prober
Wafer probers are robotic machines that manipulate
wafers as the individual dies are tested by the ATE
equipment. The prober moves the wafer underneath a
set of tiny electrical probes attached to a probe card. The
probes are connected to the electrical resources of the
ATE tester through a probe interface board (PIB).
The PIB is a specialized type of DIB board that may be
connected to the probe card through coaxial cables
and/or spring-loaded contacts called pogo pins. The PIB
and probe card serve the same purpose for the wafer
that the DIB board serves for the packaged device. They
provide a means of temporarily connecting the DUT to
the ATE tester's electrical instrumentation while testing is
performed.
How to Work
The prober informs the tester when it has placed
each new die against the probes of the probe
card.
The ATE tester then executes a series of
electrical tests on the die before instructing the
prober to move to the next die.
The handshaking between tester and prober
insures that the tester only begins testing when
a die is in position and that the prober does not
move the wafer in mid test.
Tester
Probe
Probe Card
Probe Card and Test
Board
Tester interface with DUT
(Teradyne A5xx as example below )
(Optional, has advantage of sharing DIB among various of products)
(Optional, for DUT board)
Socket, chosen based on DUT package. Refer to next page for
venders.
DUT, different devices have different package types, will be
introduced in Assembly Introduction course.
(locking mechanism to ensure DIB in position with test head ISO-pins)
(has name of DIB, LB, HIB, PIB)
Typical Wafer Probing interconnection
Probe Card and DUT Board
Probe Card
DIB/Load Board Cable
DUT/Test Board
What is Handler
Handlers are used to manipulate packaged devices in
much the same way that prober are used to manipulate
wafers.
Handler has one main purpose: to make a temporary
electrical connection between the DUT pins and the DIB
board.
In addition to providing a temporary connection to the
DUT, handlers are also responsible for sorting the good
DUTs from the bad ones based on test results from the
ATE tester. Some handlers also provide a controlled
thermal chamber where devices are allowed to "soak" for
a few minutes so they can either be cooled or heated
before testing. Since many electrical parameters shift
with temperature, this is an important handler feature.
Handler Category
Gravity Feed Handler:
MCT36xx, SESSCO, MCT 5100, RASCO (SO1000, SO2000), KUWANO, AAT,
MULTITEST (MT8501, MT8503, MT8589, MT8588, MT8704, MT9308, MT9320,
MT9918, MT9928), ADVANTEST T3333, AETRIUM, AET3300, AET5050,

Pick & Place Handler:
MT9510, EPSON (HM3500, NS6040), SYNAX 141, DELTA (Edge,Castle), ASM

Turret Handler :
ISMICA (NT16, NX16), SRM (TD246, XD206)

Note: different handler used in different package, or different change kit
required for different package in same handler.
Gravity Feed Handler
Pick & Place Handler
Turret Handler
ISMECA NX16
SRM TD246
SRM: http://www.srm.com.my
SRM XD206
Final Test
Test Kit/Station
Flat Test Kit/Station
Clamp Test Kit/Station
Typical Final Test interconnection
Test Station
and DUT Board
DIB/Load Board Cable DUT/Test Board
Typical Test Station
Handler is connected to tester via interface:
Serial port (RS232)
Parallel port ()
GPIB connection
TTL

* Handler received and delivers unit to test site, push unit
against socket, then send SOT (start of test) signal to tester;
* Tester executes program and perform testing;
* Tester send EOT (end of test) signal back to handler once
program execution is done, meanwhile tester sends binning
signal to handler based on test result;
* Handler categorize unit according to binning signal.

How handler or Probe interface with
tester ?
TTL Interface Control
Single Site Interface Control Waveform :
Suppose : All Signals are in active LOW
1st Test Prog. End 1st Test Prog. Running
SOT/START / EOW
from handler or
probe
TEST
PROGRAM
BIN 1~8 from IC
Tester
EOT / REJ from IC
Tester
1 ~ 1000ms
BIN_EOT DELAY
(Min.1ms)
Begin at 1st TP END
End at next START
Min. 1ms
2nd Test Prog. Running
EOT DELAY
EOT_BIN DELAY
Multi Site Parallel Mode Interface Control Waveform:
Suppose : All Signals are in active LOW
TTL Interface Control
JP1 START1
TEST PROGRAM
JP1 Site 1 BIN
1st Test Prog. End
1st TP. Running 2nd TP. Running
JP2 START2
JP3 START3
JP4 START4
START WAIT
S1 BIN
JP1 EOT
BIN_EOT
DELAY EOT DELAY
JP2 Site 2 BIN S2 BIN
JP3 Site 3 BIN S3 BIN
JP4 Site 4 BIN S4 BIN
JP2 EOT
JP3 EOT
JP4 EOT
S1 EOT
S2 EOT
S3 EOT
S4 EOT
EOT_BIN DELAY

marketing

systems engineers
NPBADesign

process


ATE
ATE
ATE


laser trimmingFuse Trimming
memory

PEPE
PEprocess

PETE
PE
PTE
.
PE/TE


Wafer Test waferDie
Wafer SortCP.
Package Test

Final TestFT
Quality Assurance Test Package Test
pass
Device Characterization
Pre/Post Burn-In Burn-in

Miliary Test

Incoming Inspection

Assembly Verification
FT
Failure Analysis

Accuracy - Ability to obtain true answer
Electromagnetic interference
Calibration / Ranging of instrument
Incorrect test conditions
Repeatability (a.k.a. reproducibility) - Ability to obtain
the same answer multiple times
Never changing values are suspicious
Gaussian noise - Statistical distribution
Improperly ranged instrument
Correlation - Repeatability across tester hardware
Day to day variations
Hardware variations
Accuracy, Repeatability,
and Correlation
(1/6)
AccuracyPrecision
Accuracy-

Precision-
Repeatability100mV
100.2100.3,
99.8~100.2
Resolution (Quantization Error)
ATEATE

ADCsATE
(2/6)
(3/6)
Stability

Stability

(4/6)
Correlation
Correlation
Correlation

Correlation
Correlation

Correlation
tester to bench(),
tester to tester, program to program
, DIB to DIB, day to day
.
(5/6)
Tester-to-Bench Correlation
bench
benchATE

Tester-to-Tester Correlation

Correlation
program to program Correlation
Correlation

DIB to DIB Correlation
Correlation

day to day Correlation

(6/6)
Repeatability

10

Reproducibility
ReproducibilityRepeatabilityRepeatability

Reproducibility

RepeatabilityReproducibility

Repeatability

ReproducibilityRepeatability

Time is Money!!
High-end Tester costs $2,000,000 and up.
High-end Probers / Handlers cost $500,000 and up.
1 second of test time equals 3 to 5 cents.
5 second test program @ 4 cents per second times one
million devices per quarter costs TI $800,000 per year in
profit.
Process improvements allow more and more
circuits to be placed on a single chip.
Unfortunately, smaller silicon dimensions do
not transfer into faster test times. As chip
complexity increases, so does test time.
Economics of Production Testing
The End.

Thank you!