Flip

Flop
Latches
and Flip
Flop
S-R
Flip
Flop
J-K
Flip
Flop
D-Flip
Flop
By. Sajid Hussain Qazi
Department of Electrical Engineering
MUET S.Z.A Bhutto Campus,
Khairpur
LATCHES & FLIP FLOPS
As Logic gates are the building blocks of combinatorial
circuits, latches and flip-flops are the building blocks of
sequential circuits.
Both latches and flip-flops are circuit elements whose
output depends not only on the current inputs, but also on
previous inputs and outputs. The difference between a
latch and a flip-flop is that a latch does not have a clock
signal, whereas a flip-flop always does.
LATCHES & FLIP FLOPS
Latches and flip-flops are effectively 1-bit memory cells. They
allow circuits to store data and deliver it at a later time, rather
than acting only on the inputs at the time they are given.
Devices using latches can be built to give different outputs
each time a circuit is activated, even if the same inputs are
used, and so circuits using them are referred to as "sequential
logic".
They allow for the design of counters, long-term clocks, and
complex memory systems, which cannot be created with
combinatorial logic gates alone. Latches are also used when a
device needs to behave differently depending
on previous inputs.
TRIGERRING and CLOCKING
A trigger is a control signal used to initiate an action.
In the gated latches, the trigger is the enable line. Setting
the enable HIGH allows the latch to be set or reset.
Triggers can be of two forms
1. Level Triggers (HIGH or LOW levels)
2. Edge Triggers (+ve or ve going transitions)

TRIGERRING and CLOCKING
Examining a pulse, indicates all the possible levels and
edges







TRIGERRING and CLOCKING





A level trigger means that an action is initiated on either a LOW or
HIGH level.
An edge trigger means that an action is initiated on either a positive
or negative transition.
A clock is a series of pulses (Square Waves) used to synchronize
actions. Generally the triggers are taken from the edges of the clock.

Back To Main
S-R FLIP FLOP or LATCH
An SR latch has 2 inputs, S and R. (Set and Reset)
The output is conventionally labeled Q, and "inverse
output" Q . (Having both Q and Q is called "dual
outputs").
When a signal comes into S, Q is set on and stays on until
a similar signal comes into R, upon which Q is reset to
"off". Q indicates the opposite of Q, when Q is high, Q is
low, and vice versa.
S-R FLIP FLOP or LATCH
It can be constructed from a pair of cross-
coupled NAND logic gates. The stored bit is present on the
output marked Q.
While the S and R inputs are both low, feedback maintains the
Q and outputs in a constant state, with the complement
of Q.
If S (Set) is pulsed high while R (Reset) is held low, then the Q
output is forced high, and stays high when S returns to low;
similarly, if R is pulsed high while S is held low, then the Q
output is forced low, and stays low when R returns to low.
S-R FLIP FLOP or LATCH
Typical uses include an alarm system in which a warning
light stays on after a pressure plate is activated until a
reset button is pushed, RS latches are common parts of
other circuits, including other sorts of latches.







S-R FLIP FLOP or LATCH
The R = S = 0 combination is called a restricted
combination or a forbidden state because, as both NAND
gates then output logic-1, it breaks the logical equation;
Q = .
When S=1 and R=0, Q and are at 0 and 1 respectively, hence
known as Reset condition.
When S=0 and R=1, Q and are at 1 and 0 respectively, hence
known as Set condition.
When S=1 and R=1, there will be no change in Q and ,
hence known as Hold condition.


S-R FLIP FLOP or LATCH
INPUT OUTPUT
REMARKS
S R Q

0 0 1 1 Prohibited
State
1 0 0 1 Reset
0 1 1 0 Set
1 1 0 0 Hold
DE-BOUNCING CIRCUIT
Push-button switches, toggle switches, and electro-
mechanical relays all have one thing in common:
contacts.
It's the metal contacts that make and break the circuit and
carry the current in switches and relays.
And since at least one of the contacts is on a movable
strip of metal, it has spring.
DE-BOUNCING CIRCUIT
Because the moving contacts have mass and spring with
low damping they will be "bouncy" as they make and
break circuit.
That is, when a normally open (N.O.) pair of contacts is
closed, the contacts will come together and bounce off
each other several times before finally coming to rest in a
closed position. The effect is called "contact bounce" or,
in a switch, "switch bounce"
DE-BOUNCING CIRCUIT




A simple hardware debounce circuit for a momentary
N.O. push-button switch is show in below,
DE-BOUNCING CIRCUIT
The effect of bouncing is
not acceptable in many
applications, so it can be
removed by using SR
Latch.
DE-BOUNCING CIRCUIT
Let us assume that initially
switch is resting in position A,
so R will have 0-level and S
have 1-logic, here Q output
will be zero.
Move switch to point B, here
S=0 and R=1. So Q=1 i.e +5v
in nSec time with no bouncing.
Q will remain at +5v even
after switch is not connected to
any position.
+5v
+5v
B
A
CLOCKED R-S FLIP FLOP
CLOCKED R-S FLIP FLOP
The AND gates are used to pass the Set and Reset signals
to the latch when the Enable line is asserted.
The SR-latch will operate normally when the Enable is
HIGH.
The following truth table for the gated SR latch can be
constructed using the following properties of AND gates
X.0=0
X.1=X
CLOCKED R-S FLIP FLOP
MODE OF
OPERATION
Clk/
Enable
S R Q

EFFECT ON
OUTPUT
HOLD 1 0 0 Q


No Change
RESET 1 0 1 0 1 Reset
SET 1 1 0 1 0 Set
PROHIBITED 1 1 1 1 1 Racing
CLOCKED R-S FLIP FLOP
Timing Diagram
Back To Main
DATA FLIP FLOP (D-Flip Flop)
D latch stands for Data Latch.
D latch uses only one input to set and reset the latch.
This is achieved by placing a NOT gate between the S
and R inputs of a gated SR latch.
The NOT guarantees that the unwanted R=S=1 does not
occur.
The enable controls the latching of the data.
DATA FLIP FLOP (D-Flip Flop)
Enable Data Result
0 0 No Change
0 1 No Change
1 0 Q=0
1 1 Q=1
DATA FLIP FLOP (D-Flip Flop)
Timing Diagram
DATA FLIP FLOP (D-Flip Flop)
Region Enable Data Description Q
A 0 0 Unchanged 0
B 1 1 Load Data 1
C 0 1 Unchanged 1
D 1 0 Load Data 0
E 0 1 Unchanged 0





The data is loaded into the latch in regions B & D since
Enable is HIGH.
Regions A & C & E, do nothing since Enable is LOW.
Back To Main
J-K FLIP FLOP
The JK is a widely used flip-flop.
J & K do not mean anything special.
The J is equivalent to a set., the K is equivalent to a reset.
A JK flip-flop acts like a RS flip-flop except that it does not
have a invalid state.
The R=S=1 state has been replaced with a toggle state.
Toggle means that the output (Q) will change to the opposite
state (0 to 1 or 1 to 0) after every clock transition.
The JK is an RS flip-flop with feed back from Q and /Q.
J-K FLIP FLOP
J-K FLIP FLOP
J-K FLIP FLOP
ILLUSTRATION OF TOGGLE
J-K FLIP FLOP
ILLUSTRATION OF TOGGLE
Asynchronous PRESET and
CLEAR inputs
The previous flip-flops are synchronous because data is
transferred to the flip-flops output on the clock signal.
Asynchronous inputs change the state of the flip-flop
without requiring a clock pulse.
The asynchronous inputs are normally preset and clear,
which allows the flip-flop to be set and reset.




MODE CLR PS CLK J K Q

Asyn Set 0 1 X X X 1 0
Asyn Reset 1 0 X X X 0 1
Prohibit 0 0 X X X 1 1
Master Slave J-K Flip Flop
A master-slave flip-flop is a flip-flop that responds to a
pulse rather than an edge or a level.
It consists of two flip-flops called the master and the slave.
The master flip-flop latches the inputs on the positive edge
of the clock and transfers them to the slave on the negative
edge of the clock.
They consist of two latches: a master S-R latch (S-R flip-
flop) that receives data while the input trigger clock is
HIGH, and a slave S-R latch that receives data from the
master and outputs it when the clock goes LOW
Master Slave J-K Flip Flop
Master Slave J-K Flip Flop
Master Slave J-K Flip Flop
MODE Clk J K Q
Q
RESET 0 1 0 1
SET 1 0 1 0
HOLD 0 0 NC NC
TOGGLE 1 1
Q

Q
Master Slave J-K Flip Flop
From Figure, we can see that the master latch will be loaded with the
state of the J and K inputs, whereas AND gates 1 and 2 are enabled
by a HIGH clock pulse(i.e., the master is loaded while Cp is HIGH).
When Cp goes LOW, gates 1 and 2 are disabled, but gates 3 and 4
are enabled by the HIGH from the inverter, allowing the digital state
at the master to pass through to the slave latch inputs.
When Cp goes HIGH again, gates 3 and 4 will be disabled, thus
keeping the slave latch at its current digital state. Also, with Cp
HIGH again, the master will be loaded with the digital states of the J
and K inputs, and the cycle repeats.




Master Slave J-K Flip Flop
Masterslave flip-flops are called pulse-triggered or level-triggered
devices because input data are read during the entire time that the
clock pulse is at a HIGH level.
If you analyze the logic in Figure, including the feedback lines, you
will see how the toggle operation occurs. With J=1 and K=1, lets
assume that Q=1 ( = 0).
The feedback connection from Q=1 will enable gate 2 (gate 1 is
disabled by the 0 on ), allowing the master to get reset when Cp
goes HIGH. Therefore, Q (of the slave) will toggle to a 0 when Cp
returns LOW.
With J and K still 1 and Q=0, the next time Cp is HIGH, gate 1 will
be enabled because =1 . This will set the master. Then when Cp
returns LOW, the Q output of the slave will toggle to 1.
AC Characteristics
The time taken from the triggering input transition to the
corresponding output transition.
The transitions are measured from the 50% point.
The output (Q) is measured relative to the:
1. Clock Pulse input.
2. Preset and Clear inputs.


Propagation Delay Time
AC Characteristics
Propagation Delay Time
AC Characteristics
The minimum time that the logic levels must be maintained on the
inputs prior to the clock transition.
This guarantees that the inputs are reliably clocked into the flip-flop.





Setup Time (ts)
AC Characteristics
The minimum time that the logic levels must be maintained on the
inputs after the clock transition.
This guarantees that the inputs are reliably clocked into the flip-flop.





Holding Time (th)