Under The Guidance: Prof. Dr. M.T.

GANESH KUMAR
Presented By: Ananya Devraj

Contents
Problem Definition
Introduction
Approach
Proposed Architecture
FPGA Implementation
Applications
Conclusion
References

Problem Definition
With the increase in the transistor density in a single chip, it has
led for the development of various single chip systems with multiple
heterogeneous cores. Where the design space is effectively used to
form a complex embedded system. Thus, not only providing security
to a many core system is difficult but also its effective resource
utilization provides a serious challenge to the designer.


Introduction

Increased transistor density.
Increase in number of components.
Complex & highly computational system SoC Design.
Protect Data.
Data security.


Approach

AES (Integrate) Heterogeneous many core system.
2 Approaches:
1
st
approach:
(AXIM)Platform :
AES module, NI, Internal memory, Controller.
2
nd
approach:
(AXIM)Platform :
AES module + MP , NI, DMA, Internal memory.
Proposed Architecture
Proposed Architecture
FPGA implementation
In terms of:
Resource utilization.
Speed.
Throughput.
Designs easily changed.
Easy reprogrammable.

Conclusion



Input Output
(Plain text) (Cipher text)


CPE

AXIM platform AXI Sub-system

Controller




Module
(AES based)



AXIM Platform
Applications
Mainly used for securing sensitive but unclassified
material by U.S government agencies.
Used for encrypting data's in fields like
telecommunication, financial. (Banking sectors, Private
& federal information security)


References

Integration of AES on Heterogeneous Many-Core system by Hassan
Anwar, Masoud Daneshtalab, Masoumeh Ebrahimi, Marco Ramirez,
Juha Plosila, Hannu Tenhunen, 2014 22nd Euromicro International
Conference on Parallel, Distributed, and Network-Based Processing
Y. Zhang and X. Wang, Pipelined implementation of AES encryption
based on FPGA, IEEE International Conference on Information theory
and Information Security, pp. 170-173, Dec. 2010, Beijing.
S. M. Yoo, D. Kotturi, D. W. Pan and J. Blizzar, An AES crypto chip
using a high-speed parallel pipelined architecture, Elsevier,
Microprocessor and Microsystem, vol. 29, pp. 317-236, Jan. 2005
Thank
You