Counters and Shift Rgisters

Counters & Shift Registers
Lecture 13: Sequential Logic

Counters and Registers
Counters
Introduction: Counters
Asynchronous (Ripple) Counters

Asynchronous Counters with MOD number < 2n
Asynchronous Down Counters
Cascading Asynchronous Counters
Lecture 13: Sequential Logic

Counters and Registers
Synchronous (Parallel) Counters
Up/Down Synchronous Counters
Designing Synchronous Counters
Decoding A Counter
Counters with Parallel Load
Counters are circuits that cycle through a specified
number of states.
Two types of counters:

synchronous (parallel) counters
asynchronous (ripple) counters
Ripple counters allow some flip-flop outputs to be

used as a source of clock for other flip-flops.
Synchronous counters apply the same clock to all

flip-flops.

Asynchronous counters: the flip-flops do not change
states at exactly the same time as they do not have a
common clock pulse.
Also known as ripple counters, as the input clock

pulse ripples through the counter cumulative
delay is a drawback.
n flip-flops a MOD (modulus) 2n counter. (Note: A

MOD-x counter cycles through x states.)
Output of the last flip-flop (MSB) divides the input

clock frequency by the MOD number of the counter,
hence a counter is also a frequency divider.

Example: 2-bit ripple binary counter.
Output of one flip-flop is connected to the clock input
of the next more-significant flip-flop.
HIGH
Q0
J
C
K
CLK
FF0
CLK
Q0
Q1
J
C
K
FF1
Q0
Timing diagram
Q0 0
Q1 0
00 01 10 11 00 ...

Example: 3-bit ripple binary counter.
HIGH
Q0
J
CLK
C
K
C
K
Q0
FF0
CLK
Q1
C
K
Q1
FF2
FF1
Q2
Q0
Q1
Q2
0
Recycles back to 0

Propagation delays in an asynchronous (rippleclocked) binary counter.
If the accumulated delay is greater than the clock

pulse, some counter states may be misrepresented!
CLK
Q0
Q1
Q2
tPLH
(CLK to Q0)
tPHL (CLK to Q0)

tPLH (Q0 to Q1)
tPHL (CLK to Q0)

tPHL (Q0 to Q1)
tPLH (Q1 to Q2)
10

Example: 4-bit ripple binary counter (negative-edge
triggered).
HIGH
Q0
J
CLK
Q1
C
K
C
K
FF0
Q2
C
K
FF1
FF2
Q3
C
K
FF3
CLK
1
10 11 12 13 14 15 16
Q0
Q1
Q2
Q3
11
Asyn. Counters with MOD no. < 2
States may be skipped resulting in a truncated

sequence.
Technique: force counter to recycle before going

through all of the states in the binary sequence.
Example: Given the following circuit, determine the

counting sequence (and hence the modulus no.)
C
All J, K
inputs
are 1
(HIGH).
CLK
K
Q
CLR
CLK
K
Q
CLR
CLK
K
Q
CLR
B
C
Asynchronous Counters with
MOD number < 2^n
12
Example (contd):
C
All J, K
inputs
are 1
(HIGH).
Clock
CLK
K
Q
CLR
CLK
K
Q
CLR
CLK
K
Q
CLR
B
C
1
10 11 12
A
B
C
NAND 1
Output 0
MOD number < 2^n
MOD-6 counter
produced by
clearing (a MOD-8
binary counter)
when count of six
(110) occurs.
13
Example (contd): Counting sequence of circuit (in

CBA order).
1
Temporary
state
Clock
A 0
0 1
0 1
B 0
1 1
0 0
C 0
NAND 1
Output 0
0 0
0 0
111
10 11 12
000
001
110
010
101
Counter is a MOD-6
counter.
011
100
MOD number < 2^n
14
Exercise: How to construct an asynchronous MOD-5

counter? MOD-7 counter? MOD-12 counter?
Question: The following is a MOD-? counter?

F
K
CLR
K
CLR
C
D
E
F
K
CLR
K
CLR
K
CLR
K
CLR
All J = K = 1.

MOD number < 2^n
15
Decade counters (or BCD counters) are counters

with 10 states (modulus-10) in their sequence.
They are commonly used in daily life (e.g.: utility
meters, odometers, etc.).
Design an asynchronous decade counter.

(A.C)'
HIGH
J
CLK
K
CLR
K
CLR
K
CLR
K
CLR

MOD number < 2^n
16
Asynchronous decade/BCD counter (contd).

HIGH
J
CLK
C
K
C
K
CLR
Clock
C
K
CLR
(A.C)'
C
K
CLR
CLR
10
D 0
C 0
B 0
A 0
11
NAND
output
MOD number < 2^n
17

So far we are dealing with up counters. Down
counters, on the other hand, count downward from
a maximum value to zero, and repeat.
Example: A 3-bit binary (MOD-23) down counter.

1
J
CLK
Q0
Q1
C
K Q'
C
Q'
K
Q2
C
K Q'
3-bit binary
up counter
1
J
CLK
C
Q'
K
Q0
C
K Q'
Q1
Q2
C
K Q'
3-bit binary
down counter
18

Example: A 3-bit binary (MOD-8) down counter.
000
1
J
CLK
111
001
Q0
Q1
C
K Q'
C
Q'
K
Q2
010
C
K Q'
110
011
101
100
CLK
Q0
Q1
Q2
19

Larger asynchronous (ripple) counter can be
constructed by cascading smaller ripple counters.
Connect last-stage output of one counter to the

clock input of next counter so as to achieve highermodulus operation.
Example: A modulus-32 ripple counter constructed

from a modulus-4 counter and a modulus-8 counter.
Q0
J
CLK
C
Q'
K
Q1
J
Q2
J
C
K Q'
C
Q'
K
Modulus-4 counter
Q3
Q
C
K Q'
Q4
J
C
K Q'
Modulus-8 counter
Cascading Asynchronous
Counters
20

Example: A 6-bit binary counter (counts from 0 to
63) constructed from two 3-bit counters.
A0
Count
pulse
A1
A2
A3
3-bit
binary counter
A4
A5
3-bit
binary counter
A5
A4
A3
A2
A1
A0
0
0
0
0
0
0
:
0
0
0
0
0
0
:
0
0
0
0
1
1
:
0
0
:
1
0
0
:
0
0
:
1
0
0
:
0
1
:
1
0
1
:
Counters
21

If counter is a not a binary counter, requires
additional output.
Example: A modulus-100 counter using two decade

counters.
1
CTEN Decade
counter TC
C
Q3 Q2 Q1 Q0
CLK
freq/10
CTEN Decade
freq/100
counter TC
C
Q3 Q2 Q1 Q0
freq
TC = 1 when counter recycles to 0000
Counters
22

Synchronous (parallel) counters: the flip-flops are
clocked at the same time by a common clock pulse.
We can design these counters using the sequential

logic design process (covered in Lecture #12).
Example: 2-bit synchronous binary counter (using T

flip-flops, or JK flip-flops with identical J,K inputs).
00
01
11
10
Present
state
Next
state
Flip-flop
inputs
A1 A0
0 0
0 1
1 0
1 1
A1+ A0+
0
1
1
0
1
1
0
0
TA1 TA0
0
1
1
1
0
1
1
1
23

flip-flops, or JK flip-flops with identical J,K inputs).
Present
state
Next
state
Flip-flop
inputs
A1 A0
0 0
0 1
1 0
1 1
A1+ A0+
0
1
1
0
1
1
0
0
TA1 TA0
0
1
1
1
0
1
1
1
TA1 = A0
TA0 = 1
1
J
C
Q'
K
A0
A1
C
K Q'
CLK
24

flip-flops, or JK flip-flops with identical J, K inputs).
Present
state
A2 A1 A0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
A1
A2+
0
0
0
1
1
1
1
0
Next
state
A1+ A0+
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
A2
A0
TA2 = A1.A0
A2
Flip-flop
inputs
TA2 TA1 TA0
0
0
1
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
0
1
1
1
1
A1
1
A2
A1
1
A0
A0
TA1 = A0
TA0 = 1
25

Example: 3-bit synchronous binary counter (contd).
TA2 = A1.A0
TA1 = A0
TA0 = 1
A2
A1
A0
CP
1
26

Note that in a binary counter, the nth bit (shown
underlined) is always complemented whenever
01111 10000
or
11111 00000
Hence, Xn is complemented whenever

Xn-1Xn-2 ... X1X0 = 1111.
As a result, if T flip-flops are used, then

TXn = Xn-1 . Xn-2 . ... . X1 . X0
27

Example: 4-bit synchronous binary counter.
TA3 = A2 . A1 . A0
TA2 = A1 . A0
TA1 = A0
TA0 = 1
A1.A0
1
J
C
Q'
K
A0
C
K Q'
A1
A2.A1.A0
Q
A2
C
K Q'
A3
C
K Q'
CLK
28

Example: Synchronous decade/BCD counter.
Clock pulse
Q3
Q2
Q1
Q0
Initially
1
2
3
4
5
6
7
8
9
10 (recycle)
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
T0 = 1
T1 = Q3'.Q0
T2 = Q1.Q0
T3 = Q2.Q1.Q0 + Q3.Q0
29

Example: Synchronous decade/BCD counter
(contd).
T0 = 1
T1 = Q3'.Q0
T2 = Q1.Q0
T3 = Q2.Q1.Q0 + Q3.Q0
Q0
1
T
C
Q
Q'
T
C
Q
Q'
Q1
T
C
Q2
Q'
T
C
Q3
Q'
CLK
30

Up/down synchronous counter: a bidirectional
counter that is capable of counting either up or
down.
An input (control) line Up/Down (or simply Up)

specifies the direction of counting.
Up/Down = 1 Count upward
Up/Down = 0 Count downward
31

Example: A 3-bit up/down synchronous binary
counter.
Clock pulse
0
1
2
3
4
5
6
7
Up
Q2
Q1
Q0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
TQ0 = 1
TQ1 = (Q0.Up) + (Q0'.Up' )
TQ2 = ( Q0.Q1.Up ) + (Q0'. Q1'. Up' )
Down
Up counter
TQ0 = 1
TQ1 = Q0
TQ2 = Q0.Q1
Down counter
TQ0 = 1
TQ1 = Q0
TQ2 = Q0.Q1
32

Example: A 3-bit up/down synchronous binary
counter (contd).
TQ0 = 1
TQ1 = (Q0.Up) + (Q0'.Up' )
TQ2 = ( Q0.Q1.Up ) + (Q0'. Q1'. Up' )
Q0
1
Up
T
C
Q
Q'
Q1
T
C
Q
Q'
T
C
Q2
Q'
CLK
33

Covered in Lecture #12.
Example: A 3-bit Gray code
counter (using JK flip-flops).
000
001
100
101
011
111
010
110
Present
state
Q2 Q1 Q0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Q2+
0
0
1
0
0
1
1
1
Next
state
Q1+
0
1
1
1
0
0
1
0
Q0+
1
1
0
0
0
0
1
1
JQ2 KQ2
0
X
0
X
1
X
0
X
X
1
X
0
X
0
X
0
Flip-flop
inputs
JQ1 KQ1 JQ0 KQ0
0
X
1
X
1
X
X
0
X
0
0
X
X
0
X
1
0
X
0
X
0
X
X
1
X
0
1
X
X
1
X
0
34

3-bit Gray code counter: flip-flop inputs.
Q2
Q1Q0
00
01 11
0
1
10
1
Q2
Q2
00
0 X
01 11
X X
10
X
1 1
KQ2 = Q1'.Q0'
00
0
01 11
1
X
10
X
JQ1 = Q2'.Q0
JQ2 = Q1.Q0'
Q1Q0
Q1Q0
Q2
Q1Q0
00
0 X
01 11
X
1 X
10
KQ1 = Q2.Q0
Q2
Q1Q0
00
0 1
01 11
X X
10
JQ0 = Q2.Q1 + Q2'.Q1'

= (Q2 Q1)'
Q2
Q1Q0
00
0 X
01 11
1
10
X
1 X
KQ0 = Q2.Q1' + Q2'.Q1

= Q2 Q1
35

3-bit Gray code counter: logic diagram.
JQ2 = Q1.Q0'
KQ2 = Q1'.Q0'
JQ1 = Q2'.Q0
KQ1 = Q2.Q0
Q0
JQ0 = (Q2 Q1)'

KQ0 = Q2 Q1
Q1
K Q'
Q1
K Q' '
C
K Q'
Q2
Q2
'
Q0
'
CLK
36
Decoding A Counter
Decoding a counter involves determining which state
in the sequence the counter is in.
Differentiate between active-HIGH and active-LOW

decoding.
Active-HIGH decoding: output HIGH if the counter is

in the state concerned.
Active-LOW decoding: output LOW if the counter is

in the state concerned.
Decoding A Counter
37
Decoding A Counter
Example: MOD-8 ripple counter (active-HIGH
decoding).
Clock
10
A'
B'
C'
HIGH only on
count of ABC = 000
A'
B'
C
HIGH only on
count of ABC = 001
A'
B
C'
HIGH only on
count of ABC = 010
.
.
.
HIGH only on
count of ABC = 111
A
B
C
Decoding A Counter
38
Decoding A Counter
Example: To detect that a MOD-8 counter is in state
0 (000) or state 1 (001).
A'
B'
C'
A'
B'
C
Clock
10
HIGH only on
count of ABC = 000
or ABC = 001
A'
B'
Example: To detect that a MOD-8 counter is in the

odd states (states 1, 3, 5 or 7), simply use C.
Clock
10
HIGH only on count

of odd states
Decoding A Counter
39

Counters could be augmented with parallel load
capability for the following purposes:
To start at a different state
To count a different sequence
As more sophisticated register with increment/decrement
functionality.
40

Different ways of getting a MOD-6 counter:
A4 A3 A2 A1
Load
I4 I3 I2 I1
A4 A3 A2 A1
Count = 1
Clear = 1
CP
Inputs = 0
Count = 1
Load = 0
CP
Clear
I4 I3 I2 I1
Inputs have no effect
(a) Binary states 0,1,2,3,4,5.
(b) Binary states 0,1,2,3,4,5.
A4 A3 A2 A1
A4 A3 A2 A1
Carry-out
Load
I4 I3 I2 I1
Count = 1
Clear = 1
CP
Load
I4 I3 I2 I1
1 0 1 0
Count = 1
Clear = 1
CP
0 0 1 1
(c) Binary states 10,11,12,13,14,15.
(d) Binary states 3,4,5,6,7,8.
41

4-bit counter with
parallel load.
Clear CP Load Count
Function
0
X
X
X
Clear to 0
1
X
0
0
No change
1
1
X
Load inputs
1
0
1
Next state
42
Introduction: Registers
An n-bit register has a group of n flip-flops and some
logic gates and is capable of storing n bits of
information.
The flip-flops store the information while the gates

control when and how new information is transferred
into the register.
Some functions of register:

retrieve data from register
store/load new data into register (serial or parallel)
shift the data within register (left or right)
Introduction: Registers
43
Simple Registers
No external gates.
Example: A 4-bit register. A new 4-bit data is loaded
every clock cycle.
A3
A2
A1
A0
I3
I2
I1
I0
CP
Simple Registers
44
Registers With Parallel Load

Instead of loading the register at every clock pulse,
we may want to control when to load.
Loading a register: transfer new information into the

register. Requires a load control input.
Parallel loading: all bits are loaded simultaneously.
45

Load'.A0 + Load. I0
Load
1
I0
A1
D Q
A2
D Q
A3
6
7
I3
D Q
4
5
I2
A0
2
3
I1
D Q
CLK
CLEAR
46
Shift Registers
Another function of a register, besides storage, is to
provide for data movements.
Each stage (flip-flop) in a shift register represents

one bit of storage, and the shifting capability of a
register permits the movement of data from stage to
stage within the register, or into or out of the register
upon application of clock pulses.
Shift Registers
50
Shift Registers
Basic data movement in shift registers (four bits are
used for illustration).
Data in
Data out
(a) Serial in/shift right/serial out

Data in
Data out
(b) Serial in/shift left/serial out

Data in
Data in
Data out
(c) Parallel in/serial out
Data in
Data out
(d) Serial in/parallel out

Data out
(e) Parallel in /
parallel out
(f) Rotate right
(g) Rotate left

Shift Registers
51
Serial In/Serial Out Shift Registers

Accepts data serially one bit at a time and also
produces output serially.
Serial data
input
D Q
C
Q0
D Q
C
Q1
D Q
Q2
D Q
Q3
Serial data
output
CLK
Serial In/Serial Out Shift Registers
52
Serial In/Parallel Out Shift Registers

Accepts data serially.
Outputs of all stages are available simultaneously.
Data input
D Q
D Q
D Q
D Q
CLK
Q0
Data input
CLK
Q1
Q2
Q3
SRG 4
Logic symbol
C
Q0 Q1 Q2 Q3
Serial In/Parallel Out Shift

Registers
55
Parallel In/Serial Out Shift Registers

Bits are entered simultaneously, but output is serial.
Data input
D0
D1
D2
D3
SHIFT/LOAD
D Q
C
Q0
D Q
Q1
D Q
C
Q2
Serial
data
D Q
Q3 out
C
CLK
SHIFT.Q0 + SHIFT'.D1
Parallel In/Serial Out Shift
Registers
56
Parallel In/Serial Out Shift Registers

Bits are entered simultaneously, but output is serial.
Data in
D0 D1 D2 D3
SHIFT/LOAD
CLK
SRG 4
C
Serial data out
Logic symbol
Parallel In/Serial Out Shift

Registers
57
Parallel In/Parallel Out Shift Registers

Simultaneous input and output of all data bits.
Parallel data inputs
D0
D1
D2
D3
D Q
D Q
D Q
D Q
CLK
Q0
Q1
Q2
Q3
Parallel data outputs
Parallel In/Parallel Out Shift

Registers
58
Bidirectional Shift Registers

Data can be shifted either left or right, using a control
line RIGHT/LEFT (or simply RIGHT) to indicate the
direction.
RIGHT/LEFT
Serial
data in
RIGHT.Q0 +
RIGHT'.Q2
D Q
D Q
Q1
D Q
C
Q2
D Q
Q3
Q0
CLK
59

4-bit bidirectional shift register with parallel load.
Parallel outputs
Clear
A4
A3
A2
A1
CLK
s1
s0
Serial
input for
shift-right
4x1
MUX
3 2 1 0
I4
4x1
MUX
3 2 1 0
I3
4x1
MUX
3 2 1 0
I2
Parallel inputs
4x1
MUX
3 2 1 0
I1
Serial
input for
shift-left
60

4-bit bidirectional shift register with parallel load.
Mode Control
s1
s0
0
0
1
1
0
1
0
1
Register Operation
No change
Shift right
Shift left
Parallel load
61
Shift Register Counters

Shift register counter: a shift register with the serial
output connected back to the serial input.
They are classified as counters because they give a

specified sequence of states.
Two common types: the Johnson counter and the

Ring counter.
Shift Register Counters
64
Ring Counters
One flip-flop (stage) for each state in the sequence.
The output of the last stage is connected to the D
input of the first stage.
An n-bit ring counter cycles through n states.

No decoding gates are required, as there is an output
that corresponds to every state the counter is in.
Ring Counters
65
Ring Counters
Example: A 6-bit (MOD-6) ring counter.
PRE
D Q
Q0
D Q
Q1
D Q
Q2
D Q
Q3
D Q
Q4
D Q
Q5
CLR
CLK
Clock
0
1
2
3
4
5
Q0
1
0
0
0
0
0
Q1
0
1
0
0
0
0
Q2
0
0
1
0
0
0
Q3
0
0
0
1
0
0
Q4
0
0
0
0
1
0
Q5
0
0
0
0
0
1
Ring Counters
100000
000001
010000
000010
001000
000100
66
Johnson Counters
The complement of the output of the last stage is
connected back to the D input of the first stage.
Also called the twisted-ring counter.

Require fewer flip-flops than ring counters but more
flip-flops than binary counters.
An n-bit Johnson counter cycles through 2n states.

Require more decoding circuitry than ring counter
but less than binary counters.
Johnson Counters
67
Johnson Counters
Example: A 4-bit (MOD-8) Johnson counter.
D Q
Q0
D Q
Q1
D Q
Q2
D Q
Q'
Q3'
CLR
CLK
Clock
0
1
2
3
4
5
6
7
Q0
0
1
1
1
1
0
0
0
Q1
0
0
1
1
1
1
0
0
Q2
0
0
0
1
1
1
1
0
Q3
0
0
0
0
1
1
1
1
0000
0001
1000
0011
Johnson Counters
1100
0111
1110
1111
68

Counters and Shift Rgisters

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Counters and Shift Rgisters

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Counters & Shift Registers

Lecture 13: Sequential Logic

Asynchronous (Ripple) Counters

Lecture 13: Sequential Logic

Two types of counters:

Ripple counters allow some flip-flop outputs to be

Synchronous counters apply the same clock to all

Asynchronous (Ripple) Counters

Also known as ripple counters, as the input clock

n flip-flops a MOD (modulus) 2n counter. (Note: A

Output of the last flip-flop (MSB) divides the input

Asynchronous (Ripple) Counters

Asynchronous (Ripple) Counters

Asynchronous (Ripple) Counters

Asynchronous (Ripple) Counters

Asynchronous (Ripple) Counters

Asynchronous (Ripple) Counters

If the accumulated delay is greater than the clock

tPHL (CLK to Q0)

Asynchronous (Ripple) Counters

tPHL (CLK to Q0)

Asynchronous (Ripple) Counters

Asyn. Counters with MOD no. < 2

States may be skipped resulting in a truncated

Technique: force counter to recycle before going

Example: Given the following circuit, determine the

Asyn. Counters with MOD no. < 2

Asyn. Counters with MOD no. < 2

Example (contd): Counting sequence of circuit (in

Asyn. Counters with MOD no. < 2

Exercise: How to construct an asynchronous MOD-5

Question: The following is a MOD-? counter?

Asynchronous Counters with

Asyn. Counters with MOD no. < 2

Decade counters (or BCD counters) are counters

Design an asynchronous decade counter.

Asynchronous Counters with

Asyn. Counters with MOD no. < 2

Asynchronous decade/BCD counter (contd).

Asynchronous Down Counters

Example: A 3-bit binary (MOD-23) down counter.

Asynchronous Down Counters

Asynchronous Down Counters

Asynchronous Down Counters

Cascading Asynchronous Counters

Connect last-stage output of one counter to the

Example: A modulus-32 ripple counter constructed

Cascading Asynchronous Counters

Cascading Asynchronous Counters

Example: A modulus-100 counter using two decade

TC = 1 when counter recycles to 0000

Synchronous (Parallel) Counters

We can design these counters using the sequential

Example: 2-bit synchronous binary counter (using T

Synchronous (Parallel) Counters

Synchronous (Parallel) Counters

Synchronous (Parallel) Counters

Synchronous (Parallel) Counters

Synchronous (Parallel) Counters

Synchronous (Parallel) Counters

Synchronous (Parallel) Counters

Synchronous (Parallel) Counters

Hence, Xn is complemented whenever

As a result, if T flip-flops are used, then