FET ( Field Effect Transistor)

Few important advantages of FET over conventional Transistors

1.

2.

Unipolar device i. e. operation depends on only one type of

charge carriers (h or e)
Voltage controlled Device (gate voltage controls drain
current)

3.

Very high input impedance (109-1012 )

4.

Source and drain are interchangeable in most Low-frequency

applications

5.

Low Voltage Low Current Operation is possible (Low-power

consumption)
Less Noisy as Compared to BJT
No minority carrier storage (Turn off is faster)
Self limiting device
Very small in size, occupies very small space in ICs
Low voltage low current operation is possible in MOSFETS
Zero temperature drift of out put is possiblek

6.
7.
8.
9.
10.
11.

Types of Field Effect Transistors

(The Classification)

FET

JFET

MOSFET (IGFET)

Enhancement
MOSFET
n-Channel
EMOSFET

p-Channel
EMOSFET

n-Channel JFET
p-Channel JFET

Depletion
MOSFET
n-Channel
DMOSFET

p-Channel
DMOSFET

The Junction Field Effect Transistor (JFET)

Figure: n-Channel JFET.

SYMBOLS

Gate

Gate

Gate

Source

n-channel JFET

Drain

Drain

Drain

Source
n-channel JFET
Offset-gate symbol

Source
p-channel JFET

Biasing the JFET

Figure: n-Channel JFET and Biasing Circuit.

Operation of JFET at Various Gate Bias Potentials

Figure: The nonconductive depletion region becomes broader with increased reverse bias.
(Note: The two gate regions of each FET are connected to each other.)

Operation of a JFET
Drain

N
Gate
+

Source

+
-

Output or Drain (VD-ID) Characteristics of n-JFET

Figure: Circuit for drain characteristics of the n-channel JFET and its Drain characteristics.

V
V

DS
P
GS

Non-saturation (Ohmic) Region:

The drain current is given by

V
I

DS

DS

DSS
V2
P

V
V
GS
P

DSS
V2
P

V2

V V
DS
V
GS
P DS
2

V
V
DS
P
GS

Saturation (or Pinchoff) Region:

I

2I

V
2

GS
and I
I
1

DS
DSS
V

Where, IDSS is the short circuit drain current, VP is the pinch off voltage

Simple Operation and Break down of n-Channel JFET

Figure: n-Channel FET for vGS = 0.

N-Channel JFET Characteristics and Breakdown

Break Down Region

Figure: If vDG exceeds the breakdown voltage VB, drain current increases rapidly.

VD-ID Characteristics of EMOS FET

Locus of pts where VDS VGS VP

Saturation or Pinch
off Reg.

Figure: Typical drain characteristics of an n-channel JFET.

Transfer (Mutual) Characteristics of n-Channel JFET

GS
I
I
1

DS
DSS
V

IDSS

VGS (off)=VP

Figure: Transfer (or Mutual) Characteristics of n-Channel JFET

JFET Transfer Curve

This graph shows the value of ID for a given
value of VGS

Biasing Circuits used for JFET

Fixed bias circuit

Self bias circuit
Potential Divider bias circuit

JFET (n-channel) Biasing Circuits

For Fixed Bias Circuit
Applying KVL to gate circuit we get

V
1 GS
I I
DS
DSS
V
P

VGG I G RG VGS VGS Fixed , I G 0

and

VGS

I DS I DSS 1
VP

and VDS VDD I DS RD

Where, Vp=VGS-off & IDSS is Short ckt. IDS

For Self Bias Circuit

VGS I DS RS 0
I DS

VGS

RS

JFET Biasing Circuits Count

or Fixed Bias Ckt.

JFET Self (or Source) Bias Circuit

GS
and I
I
1

DS
DSS
V

GS
I
1

DSS
V

GS
R
S

V
V

GS
GS
I
1

V
DSS
V

P
P

VGS
R 0

This quadratic equation can be solved for VGS & IDS

The Potential (Voltage) Divider Bias

GS
I
1

DSS
V

GS

Solving this quadratic equation gives V

GS

and I

DS

A Simple CS Amplifier and Variation in IDS with Vgs

FET Mid-frequency Analysis:

VDD

A common source (CS) amplifier is shown

to the right.

RD
R1

io

The mid-frequency circuit is drawn as follows:

the coupling capacitors (Ci and Co) and the
bypass capacitor (CSS) are short circuits
short the DC supply voltage (superposition)
replace the FET with the hybrid-p model
The resulting mid-frequency circuit is shown below.

is

ii

+
vs

ii
Rs
+
vs

RTh

Ci

vi

io
+

gmvp

rd

RD

RL

vo
_

_
s

mid-frequency CE amplifier circuit

Analysis of the CS mid-frequency circuit above yields:

A vi =

vo
= -g m R 'L , where R 'L = rd R D R L
vi

A vs =

Zi =

vi
= R Th , where R Th = R 1 R 2
ii

AI =

Zo =

vo
io

AP =

= rd R D
seen by R L

Zi

vo
= A vi

vs
R s + Zi

io
= A vi
ii

Zi

RL

po
= A vi A I
pi

vo

R2
RSS

vi = vp

+
+

Co

RL

VDD

CSS

FET Mid-frequency Analysis:

VDD

A common source (CS) amplifier is shown

to the right.

RD
R1

io
D

ii

The mid-frequency circuit is drawn as follows:

the coupling capacitors (Ci and Co) and the
bypass capacitor (CSS) are short circuits
short the DC supply voltage (superposition)
replace the FET with the hybrid-p model
The resulting mid-frequency circuit is shown below.
is

ii

+
vs
_

vi
_
_

rd

io

RD

RL

vo
_

_
s

mid-frequency CE amplifier circuit

Analysis of the CS mid-frequency circuit above yields:

A vi =

vo
= -g m R 'L , where R 'L = rd R D R L
vi

A vs =

Zi
vo
= A vi

vs
R s + Zi

Zi =

vi
= R Th , where R Th = R 1 R 2
ii

AI =

Z
io
= A vi i
ii
RL

Zo =

vo
io

AP =

po
= A vi A I
pi

= rd R D
seen by R L

vo

R2
RSS

+
gmvp

Ci

RL

vs

vi = vp

Co

Rs

+
RTh

VDD

CSS

Procedure: Analysis of an FET amplifier at mid-frequency:

1) Find the DC Q-point. This will insure that the FET is operating in the saturation
region and these values are needed for the next step.
2) Find gm. If gm is not specified, calculate it using the DC values of VGS as follows:
gm =

2I
I D
= DSS
VGS - VP
VGS
VP2

gm =

I D
= K VGS - VT
VGS

(for JFET's and DM MOSFET's)

(for EM MOSFET's)

(Note: Uses DC value of VGS )

3) Calculate the required values (typically Avi, Avs, AI, AP, Zi, and Zo. Use the formulas for
the appropriate amplifier configuration (CS, CG, CD, etc).

PE-Electrical Review Course - Class 4 (Transistors)

18 V

Example 7:
Find the mid-frequency values for Avi, Avs, AI, AP, Zi,
and Zo for the amplifier shown below. Assume that
Ci, Co, and CSS are large.
Note that this is the same biasing circuit used in Ex. 2,
so VGS = -0.178 V.
The JFET has the following specifications:
IDSS = 4 mA, VP = -1.46 V, rd = 50 k

18 V

500
800 k

io
D

ii
10 k

+
vs

Co

+
+

Ci

S
8k

vi
_

2k

vo

400 k

CSS

VDD

FET Amplifier Configurations and

Relationships:

VDD

RD
R1

io
D

ii

CS

Co

Rs

Ci

RL

vs

vo

CSS

RSS

_
Common Source (CS) Amplifier
ii

S
+

-g m R

R 'L

rd R D R L

Zi

R Th

Zo

rd R D

io

Ci
G

vi

A vi

RD

RSS

RL

R1
_

C2

vo
_

R2

VCC

A vs
Common Gate (CG) Amplifier

VDD

VDD

AI

R1

AP

ii
Rs
+
vs

gmR

'
L

rd R D R L
R SS

1
gm

CD
g m R 'L
1 g m R 'L
R SS R L
R Th

Co

+
vs

'
L

R2

vi
_

Rs

CG

rd R D

R SS

1
gm

Zi
Zi
Zi
A vi
A
A
vi
vi

R
+
Z
R
+
Z
R
+
Z
i
i
i
s
s
s
Z
A vi i
RL
A vi A I

Z
A vi i
RL
A vi A I

Z
A vi i
RL
A vi A I

+
vi

Ci

Co

R2
R SS

where R Th = R1 R 2

io

_
Common Drain (CD) Amplifier (also called source follower)

+
RL

vo
_

Note: The biasing circuit is the same for each amp.

Figure: Circuit symbol for an enhancement-mode n-channel MOSFET.

Figure: n-Channel Enhancement MOSFET showing channel length L and channel width W.

Figure: For vGS < Vto the pn junction between drain and body is reverse biased and i D=0.

Figure: For vGS >Vto a channel of n-type material is induced in the region under the gate.
As vGS increases, the channel becomes thicker. For small values of vDS ,iD is proportional to vDS.
The device behaves as a resistor whose value depends on vGS.

Figure: As vDS increases, the channel pinches down at the drain end and iD increases more slowly.
Finally for vDS> vGS -Vto, iD becomes constant.

Current-Voltage Relationship of
n-EMOSFET

Locus of points where

Figure: Drain characteristics

Figure: This circuit can be used to plot drain characteristics.

Figure: Diodes protect the oxide layer from destruction by static electric charge.

Figure: Simple NMOS amplifier circuit and Characteristics with load line.

Figure: Drain characteristics and load line

Figure vDS versus time for the circuit of Figure 5.13.

Figure Fixed- plus self-bias circuit.

Figure Graphical solution of Equations (5.17) and (5.18).

Figure Fixed- plus self-biased circuit of Example 5.3.

Figure The more nearly horizontal bias line results in less change in the Q-point.

Figure Small-signal equivalent circuit for FETs.

Figure FET small-signal equivalent circuit that accounts for the dependence of iD on vDS.

Figure Determination of gm and rd. See Example 5.5.

Figure Common-source amplifier.

For drawing an a c equivalent circuit of Amp.

Assume all Capacitors C1, C2, Cs as short
circuit elements for ac signal
Short circuit the d c supply
Replace the FET by its small signal model

Analysis of CS Amplifier
A C Equivalent Circuit

Simplified A C Equivalent Circuit

Voltage gain, A
v

v i R g v
o

m gs

v
R

gs
L

Input imp., Z R R R
in

A o g R , R R r
v v
m L
L
D d
gs

Out put imp., Z r R

o

r R

d D

r R
d

Analysis of CS Amplifier with Potential Divider Bias

Av gm(rd || RD)

This is a CS amplifier configuration therefore the

input is on the gate and the output is on the drain.

Zo rd || RD

Av gm(rd || RD)
Av gmRD, r 10R
d

Zi R1 || R2

Zo RD

rd 10RD

Figure vo(t) and vin(t) versus time for the common-source amplifier of Figure 5.28.

An Amplifier Circuit using MOSFET(CS Amp.)

Figure Common-source amplifier.

A small signal equivalent circuit of CS Amp.

Figure Small-signal equivalent circuit for the common-source amplifier.

Figure vo(t) and vin(t) versus time for the common-source amplifier of Figure 5.28.

Figure Gain magnitude versus frequency for the common-source amplifier of Figure 5.28.

Figure Source follower.

Figure Small-signal ac equivalent circuit for the source follower.

Figure Equivalent circuit used to find the output resistance of the source follower.

Figure Common-gate amplifier.

Figure See Exercise 5.12.

Figure Drain current versus drain-to-source voltage for zero gate-to-source voltage.

Figure n-Channel depletion MOSFET.

Figure Characteristic curves for an NMOS transistor.

Figure Drain current versus vGS in the saturation region for n-channel devices.

Figure p-Channel FET circuit symbols. These are the same as the circuit symbols for n-channel devices,
except for the directions of the arrowheads.

Figure Drain current versus vGS for several types of FETs. iD is referenced into the drain terminal
for n-channel devices and out of the drain for p-channel devices.