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A and B metal
C semiconductor or insulator
Semiconductors
Room-temperature thermal energy or excitation from
visible-light photons can give electrons enough energy
for "jumping" from the valence into the conduction
band
Energy gap of 1.12 eV (silicon), 0.67 eV (germanium),
and 1.42 eV (gallium arsenide)
Insulators
Insulators have significantly wider energy bandgaps
Room temperature thermal energy is not large enough
to place electrons in the conduction band
9.0 eV (SiO2), 5.47 eV (diamond), and 5.0 eV (Si3N4)
Ev - Maximum
energy of the
valence band
Ec - Minimum
energy of the
conduction band
Eg - Width of the
energy bandgap
EF Fermi level
Represents the maximum energy of an electron in the
material at zero degree Kelvin
At that temperature, all the allowed energy levels
below the Fermi level are occupied, and all the
energy levels above it are empty
Intrinsic semiconductor
A semiconductor is said to be "intrinsic" if the
vast majority of its free carriers (electrons and
holes) originate from the semiconductor atoms
themselves
In that case if an electron receives enough
thermal energy to "jump" from the valence band
to the conduction band, it leaves a hole behind
in the valence band
Every hole in the valence band corresponds to
an electron in the conduction band, and the
number of conduction electrons is exactly equal
to the number of valence holes, p=n=ni
ni versus temperature
Extrinsic semiconductor
The silicon used in the semiconductor industry
has a purity level of 99.9999999%
One can, however, intentionally introduce in
silicon trace amounts of elements which are
close to silicon in the periodic table, such as
those located in columns III (boron) or V
(phosphorus, arsenic)
If, for instance, an atom of arsenic is substituted
for a silicon atom, it will form four bonds by
sharing four electrons with the neighboring
silicon atoms
Donor impurity
Acceptor impurity
Classes of semiconductors
Intrinsic: no = po = ni
n-type: no > po, since Nd > Na
p-type: no < po, since Nd < Na
Compensated: no=po=ni, w/ Na- = Nd+ > 0
Note: n-type and p-type are usually partially
compensated since there are usually some
opposite- type dopants
n Na p Nd
Electron and hole concentration in N type
semiconductor
2
ni
n N d and p
Nd
Electron and hole concentration in P type
semiconductor
n Na
and
2
i
n
n
Na
F=Ei-EF=Fermi potential
F=Ei-EF=Fermi potential
P-N junction
qVbi = q(n
q p < 0
-xpc
-xp 0
p)
q n > 0
Ec
EfN
Efi
Ev
xnc
Drift Current
The drift current density (amp/cm2) is
given by the point form of Ohm Law
J = (nqmn+pqmp)(Exi+ Eyj+ Ezk), so
J = (sn + sp)E = sE, where
s = nqmn+pqmp defines the conductivity
The net current is
I J dS
MOSFET or IGFET
MOS (Metal-OxideSemiconductor)
MOS materials
ox
tox
A - capacitor area,
Q
VG s G
Cox
+
s
_
QG QC 0
QG
QC
ox - permittivity of oxide
QG
QG
Cox ox
; Cox
A
A
tox
QC
VG s
Cox
MOS structure
MOS capacitor
Two-terminal
semiconductor device
A metal contact
separated from the
semiconductor by a
dielectric insulator
Utilizes doped silicon as
the substrate and its
native oxide, silicon
dioxide, as the insulator
MOS capacitor
The thickness of the oxide
typically varies between 5
to 50 nm
The semiconductor
chosen for the example is
P-type silicon, which
corresponds to the
substrate of an n-channel
device
Assume work functions
are same
Accumulation
Negative bias is applied to the metal
gate while the silicon substrate is
grounded
Structure behaves like a parallel-plate
capacitor where the two electrodes are
the silicon and the metal, and the oxide is
the insulator between them.
Accumulation layer
The charge in the
silicon can also be
considered a surface
charge
Its thickness is
approximately 10
nanometers
This thin, hole-rich
layer is called an
accumulation layer
Depletion
Small positive bias is applied
to the gate
Holes near the silicon surface
are repelled by the gate.
Depletion layer
The gate charge is a surface
charge, but the charge in the
silicon is not
Depletion charge extends to a
non-negligible depth into the
silicon
The depth up to which holes
are repelled is called the
depletion depth (xd)
Inversion
If a larger positive
voltage is applied to
the gate the surface
potential will continue
to increase
The hole concentration
near the surface
decreases while the
electron concentration
increases, according
to the following
relationships:
Inversion layer
G
QG
- - - - - - - - - - VGB
Qo
+
+
+
+
++++++++++++++
Holes
QC
s 0
+ accumulate in
the p-type semiconductor
surface
G
QG
+ + + + + + + + +
VGB
Qo
+
- -- - - -Q - -- - - +
0 s F
Holes evacuate from the P
semiconductor surface and
acceptor ion charges
become uncovered
Qo
+
- -- - ---Q - -- -- -- - - - - - +
VGB VFB
QC 0
s F
electrons
surface!
approach the
Strong inversion
If the gate voltage is increased further the
electron surface concentration increases up to a
point where n(x=0) becomes equal to Na, which
is the original hole concentration in the substrate
When S=2.F condition is met semiconductor is
said to be in strong inversion
Charges in semiconductor
Threshold voltage
There are twenty + in the region
If we want to invert the region with
First remove twenty +
Then put twenty more
by putting twenty
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Threshold voltage
Consider P type substrate
Suppose you want to invert a region in that
substrate (two step process)
Remove the holes in that region by putting
electrons
No. of holes doping concentration (Ei-EF)
Threshold voltage
Threshold voltage V = VT, corresponding to the
onset of the strong inversion
Strong inversion occurs when the surface
potential s becomes equal to 2b
Poly gate
We have so far assumed that the Fermi level of
the metal gate was equal to that of the silicon. In
practice this is not the case
In modern devices the gate material is not an
actual metal, but heavily doped polycrystalline
silicon, also called poly silicon
The doping concentration used for that material
is so high (1020/cm3) that it can be considered as
a metal, for all practical purposes.
Ec
Efi
EfP
Ev
qVbi = q(n
q p < 0
-xpc
-xp 0
p)
q n > 0
Ec
EfN
Efi
Ev
xnc
Eo
affinity)
affinity)
(work function)
Ef
q F
qc (electron
Eo
Ec
Ei
Ev
P type semiconductor
(work function)
Ef
q F
Ec
Ei
Ev
N type semiconductor
MOS-Accumulation region
Charge carriers same as that of substrate type
getting accumulated near Si-SIO2 interface
A MOS structure with a p-type semiconductor
will enter the accumulation regime of operation
when the voltage applied between the metal and
the semiconductor is more negative than the flatband voltage
If VFB is +0.5 V then accumulation region is below
+0.5 V
If VFB is -0.25 V then accumulation region is below
-0.25 V
Interface traps
Presence of Si-SiO2 interface at the silicon surface
introduces perturbation to the periodic crystal
structure of the semiconductor
Causes some Si-Si bonds to be unfulfilled or "dangling"
Threshold voltage
The flat-band voltage must be added to the
expression for the threshold voltage calculated
previously in order to accurately describe the
actual, "non-ideal" threshold voltage
Controlling VTH
Depletion-mode devices will have an inversion
layer when the gate voltage is equal to zero
These devices are sometimes referred to as "normally
on".
MOS capacitance
In a MOS capacitor, the metal contact and the
neutral region in the doped semiconductor
substrate are separated by the insulator layer,
the channel, and the depletion region
Measuring capacitance
low-frequency
ac signal
DC bias
Capacitance in accumulation
When the gate voltage
is negative an
accumulation layer is
present
As the gate voltage
varies a corresponding
OX
variation of the
C
COX Farad / area
tOX
accumulation charge
occurs, and the
Capacitance is
capacitance of the
independent
structure is equal to Cox
of gate voltage
Capacitance in depletion
When the gate voltage is
increased the silicon
surface becomes
depleted, and the
variations of gate voltage
induce variations of the
depletion charge
The value of the
capacitance is then
given by the series
combination of the gate
and depletion region
capacitances
Capacitance decreases
with gate voltage
Capacitance in inversion
As the gate voltage is further increased an
inversion layer is formed and variations of gate
voltage give rise to variations of inversion
charge and thus the measure capacitance is
again equal to COX
OX
C
COX Farad / area
tOX
Capacitance is
independent
of gate voltage
(EF-Ei) factor
Positive for n type,
negative for p type
and zero for intrinsic
In other words,
if (EF-Ei) is positive
then in that region we
have more no. of
electrons
if (EF-Ei) is negative
then in that region we
have more no. of holes
If EF=Ei, then no, of
holes = no. of
electrons
Threshold voltage
Consider P type substrate
Suppose you want to invert a region in that
substrate (two step process)
Remove the holes in that region by putting
electrons
No. of holes doping concentration (Ei-EF)