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MOS capacitor operation

Energy bands of a crystal


In a single atom, electrons occupy discrete
energy levels
What happens when a large number of atoms
are brought together to form a crystal?

Permitted energy levels - Silicon

Valence and conduction bands

A and B metal
C semiconductor or insulator

Semiconductor and insulator


Distinction between insulator and semiconductor
Based on the value of the energy gap

Semiconductors
Room-temperature thermal energy or excitation from
visible-light photons can give electrons enough energy
for "jumping" from the valence into the conduction
band
Energy gap of 1.12 eV (silicon), 0.67 eV (germanium),
and 1.42 eV (gallium arsenide)

Insulators
Insulators have significantly wider energy bandgaps
Room temperature thermal energy is not large enough
to place electrons in the conduction band
9.0 eV (SiO2), 5.47 eV (diamond), and 5.0 eV (Si3N4)

Ev - Maximum
energy of the
valence band
Ec - Minimum
energy of the
conduction band
Eg - Width of the
energy bandgap
EF Fermi level
Represents the maximum energy of an electron in the
material at zero degree Kelvin
At that temperature, all the allowed energy levels
below the Fermi level are occupied, and all the
energy levels above it are empty

Fermi level in semiconductor and insulator


In an insulator or a semiconductor, we know that
the valence band is full of electrons, and the
conduction band is empty at 0 K
Therefore, the Fermi level lies somewhere in the
bandgap, between EC and EV
In a metal, the Fermi level lies within an energy
band

Understanding electron and hole concept

In this water analogy,


A drop of water - an electron
A bubble or absence of water - a hole

Hence, a hole is equivalent to a missing electron in


the crystal valence band
A hole is not a particle and it does not exist by itself

It draws its existence from the absence of an


electron in the crystal, just like a bubble in a pipe
exists only because of a lack of water
Holes can move in the crystal through successive
"filling" of the empty space left by a missing electron
The hole carries a positive charge +q, as the
electron carries a negative charge q (q=1.6x1019
Coulomb)

Effective mass of the electron in a crystal


The fact that the electron is in a crystal will
influence its response to an applied force
As a result, the apparent, "effective" mass of the
electron in a crystal will be different from that of
an electron in a vacuum.

Density of states and Fermi probability

Intrinsic semiconductor
A semiconductor is said to be "intrinsic" if the
vast majority of its free carriers (electrons and
holes) originate from the semiconductor atoms
themselves
In that case if an electron receives enough
thermal energy to "jump" from the valence band
to the conduction band, it leaves a hole behind
in the valence band
Every hole in the valence band corresponds to
an electron in the conduction band, and the
number of conduction electrons is exactly equal
to the number of valence holes, p=n=ni

Intrinsic Fermi energy level


Ei = (EC+EV)/2
One can generally consider that it lies right in the
middle of the energy bandgap

ni versus temperature

Extrinsic semiconductor
The silicon used in the semiconductor industry
has a purity level of 99.9999999%
One can, however, intentionally introduce in
silicon trace amounts of elements which are
close to silicon in the periodic table, such as
those located in columns III (boron) or V
(phosphorus, arsenic)
If, for instance, an atom of arsenic is substituted
for a silicon atom, it will form four bonds by
sharing four electrons with the neighboring
silicon atoms

Donor impurity

A Arsenic atom introduces an extra electron in crystal


An electron is released by Arsenic atom and it moves
freely in the crystal

Jump of an electron from donor energy level (Ed)

Introduction of a donor atom in silicon


Donor atoms phosphorus (P) or arsenic (As)
Gives rise to a permitted energy level in the
bandgap
Located a few meV below the bottom of the
conduction band
At very low temperature contains the electrons which
can be given by the impurity atoms to the crystal
At room temperature these electrons possess enough
thermal energy (equal to kT/q = 25.6 meV) to break
free from the impurity atoms and move freely in the
crystal or, in other words, it can "jump" from the
energy level introduced by the impurity into the
conduction band

When an electron moves away from a donor


atom, such as arsenic (As), the atom becomes
ionized and carries a positive charge, +q (refer
previous figure)

Acceptor impurity

A Boron atom introduces a missing electron in crystal


A hole is released by boron atom and it moves
freely in the crystal

Introduction of an acceptor atom in silicon


Acceptor atom - boron (B)
Gives rise to a permitted energy level in the
bandgap
This level is located a few meV above the top of the
valence band
At room temperature electrons in the top of the valence
band possess enough thermal energy to "jump" into the
energy levels created by the impurity atoms (or: valence
electrons are "captured" by acceptor atoms), which gives
rise to holes in the valence band.
These holes are free to move in the crystal

When an electron is captured by an acceptor atom,


a hole is thus released in the crystal, and the
acceptor atom (boron) becomes ionized and
carries a negative charge, -q (refer previous figure)

Main elements used in semiconductor


technology

Classes of semiconductors

Intrinsic: no = po = ni
n-type: no > po, since Nd > Na
p-type: no < po, since Nd < Na
Compensated: no=po=ni, w/ Na- = Nd+ > 0
Note: n-type and p-type are usually partially
compensated since there are usually some
opposite- type dopants

Charge neutrality under thermodynamic


equilibrium

n Na p Nd
Electron and hole concentration in N type
semiconductor
2
ni
n N d and p
Nd
Electron and hole concentration in P type
semiconductor

n Na

and

2
i

n
n
Na

Position of the Fermi Level


Efi is the Fermi level
when no = po (often
denoted as Ei )

Calculation of Fermi level N Type


semiconductor

F=Ei-EF=Fermi potential

Calculation of Fermi potential N Type


semiconductor

Calculation of Fermi level P Type


semiconductor

F=Ei-EF=Fermi potential

Calculation of Fermi potential P Type


semiconductor

Fermi levels in P and N type semiconductors

P-N junction

Depletion region in P-N junction

Band diagram for


+
p -n jctn* at Va = 0
Ec
Efi
EfP
Ev

qVbi = q(n

q p < 0

-xpc

-xp 0

p)

q n > 0

*Na > Nd -> |p| > n

p-type for x<0

n-type for x>0


xn

Ec
EfN
Efi
Ev

xnc

Drift Current
The drift current density (amp/cm2) is
given by the point form of Ohm Law
J = (nqmn+pqmp)(Exi+ Eyj+ Ezk), so
J = (sn + sp)E = sE, where
s = nqmn+pqmp defines the conductivity
The net current is

I J dS

Drift current resistance


Given: a semiconductor resistor with
length, l, and cross-section, A. What is the
resistance?
Conductivity, s = nqmn + pqmp
So the resistivity,
r = 1/s = 1/(nqmn + pqmp)

Drift current resistance (cont.)


Consequently, since
R = rl/A
R = (nqmn + pqmp)-1(l/A)
For n >> p, (an n-type extrinsic s/c)
R = l/(nqmnA)
For p >> n, (a p-type extrinsic s/c)
R = l/(pqmpA)

MOSFET or IGFET

N-channel MOS transistor

MOSFET with gate voltage zero


The gate voltage is equal to zero while the P-type
substrate and the source are grounded
The drain is connected to a positive voltage
Since the source and the substrate are at the
same potential there is no current flow in the
source-substrate junction
The drain-substrate junction is reverse biased and
except for a small negligible reverse leakage
current no current flows in that junction either
Under these conditions there is no channel
formation, and therefore, no current flow from
source to drain.

MOSFET current vs voltage characteristics

MOS (Metal-OxideSemiconductor)

Assume work function of metal and


semiconductor are same.

MOS materials

The ideal two-terminal MOS structure


A ox
V (VFB=0)
C
G

ox

tox

A - capacitor area,

Q
VG s G
Cox

+
s
_

QG QC 0

QG

QC

tox - oxide thickness

ox - permittivity of oxide

QG

QG
Cox ox

; Cox

A
A
tox

QC
VG s
Cox

Example: oxide capacitance


(a) Calculate the oxide capacitance per unit area for
tox= 5 and 20 nm assuming ox = 3.90, where 0=
8.8510-14 F/cm is the permittivity of free space. (b)
Determine the area of a 1pF metal-oxide-metal
capacitor for the two oxide thicknesses given in
(a).
Answer: (a) =690 nF/cm2 = 6.9 fF/mm2 for tox=5 nm
and = 172 nF/cm2= 1.7 fF/mm2 for tox= 20 nm. The
capacitor areas are 145 and 580 mm2 for oxide
thicknesses of 5 and 20 nm, respectively.

MOS structure

Shown is the semiconductor substrate with a thin oxide layer


and a top metal contact, also referred to as the gate.
A second metal layer forms an Ohmic contact to the back of the
semiconductor, also referred to as the bulk.
The structure shown has a p-type substrate.
We will refer to this as an n-type MOS capacitor since the
inversion layer contains electrons.

Structure and principle of operation


To understand the different bias modes of an
MOS we consider 3 different bias voltages.
(1) below the flatband voltage, VFB
(2) between the flatband voltage and the
threshold voltage, VT, and
(3) larger than the threshold voltage.
These bias regimes are called the
accumulation, depletion and inversion mode
of operation.

Structure and principle of


operation

Charges in a MOS structure under accumulation,


depletion and inversion conditions

Schematic illustration of a generic field effect


transistor
This device can be
viewed as a combination
of two orthogonal twoterminal devices

MOS capacitor
Two-terminal
semiconductor device
A metal contact
separated from the
semiconductor by a
dielectric insulator
Utilizes doped silicon as
the substrate and its
native oxide, silicon
dioxide, as the insulator

Siliconsilicon dioxide system,


the density of surface states at the oxide
semiconductor interface is very low compared to the
typical channel carrier density in a MOSFET.
Insulating quality of the oxide is quite good

MOS capacitor
The thickness of the oxide
typically varies between 5
to 50 nm
The semiconductor
chosen for the example is
P-type silicon, which
corresponds to the
substrate of an n-channel
device
Assume work functions
are same

Accumulation
Negative bias is applied to the metal
gate while the silicon substrate is
grounded
Structure behaves like a parallel-plate
capacitor where the two electrodes are
the silicon and the metal, and the oxide is
the insulator between them.

The application of the bias gives rise


to a negative charge on the gate
This is a surface charge in the metal,
located at the metaloxide interface
An equal charge of opposite sign
appears at the surface of the silicon, at
the silicon-oxide interface

Accumulation layer
The charge in the
silicon can also be
considered a surface
charge
Its thickness is
approximately 10
nanometers
This thin, hole-rich
layer is called an
accumulation layer

Depletion
Small positive bias is applied
to the gate
Holes near the silicon surface
are repelled by the gate.

Because the acceptor doping


atoms cannot move in the
silicon lattice a negative
charge appears underneath
the gate oxide
Similarly a positive charge of
equal magnitude can be found
in the gate electrode, at the
metal-oxide interface

Depletion layer
The gate charge is a surface
charge, but the charge in the
silicon is not
Depletion charge extends to a
non-negligible depth into the
silicon
The depth up to which holes
are repelled is called the
depletion depth (xd)

Inversion
If a larger positive
voltage is applied to
the gate the surface
potential will continue
to increase
The hole concentration
near the surface
decreases while the
electron concentration
increases, according
to the following
relationships:

Inversion layer

Electron surface concentration = Hole surface concentration


when Ei coincides with EF.
This happens S= F=(KT/q) ln (Na/ni)

Regions of operation of the MOSFET:


Accumulation (p-substrate)
VGB VFB
QC 0

G
QG
- - - - - - - - - - VGB

Qo
+
+
+
+
++++++++++++++
Holes
QC

s 0

+ accumulate in
the p-type semiconductor
surface

Regions of operation of the MOSFET:


Depletion (p-substrate)
VGB VFB
QC 0

G
QG
+ + + + + + + + +
VGB

Qo
+

- -- - - -Q - -- - - +

0 s F
Holes evacuate from the P
semiconductor surface and
acceptor ion charges
become uncovered

F = Fermi potential (defined in p-n


junction lecture i.e. Ei-EF)

Regions of operation of the MOSFET:


Inversion (p-substrate)
G
QG
+ + + + + + + + +
VGB

Qo
+

- -- - ---Q - -- -- -- - - - - - +

VGB VFB
QC 0

s F

electrons
surface!

approach the

Strong inversion
If the gate voltage is increased further the
electron surface concentration increases up to a
point where n(x=0) becomes equal to Na, which
is the original hole concentration in the substrate
When S=2.F condition is met semiconductor is
said to be in strong inversion

Band diagrams in semiconductor

Weak inversion and strong inversion


weak inversion:
b < s < 2b
Strong inversion:
s=2b
Flat band condition:
s=0
Accumulation
condition:
s < 0
Depletion:
0 < s < b

Charges in semiconductor

Charge versus band bending/surface


potential in semiconductor

Threshold voltage
There are twenty + in the region
If we want to invert the region with
First remove twenty +
Then put twenty more

by putting twenty
-

+
+
+

+
+

+
+

+
+

+
+

+
+
+

+
+

+
+

Threshold voltage
Consider P type substrate
Suppose you want to invert a region in that
substrate (two step process)
Remove the holes in that region by putting
electrons
No. of holes doping concentration (Ei-EF)

Put some more electrons in that region


How many more electrons doping concentration
(Ei-EF)

Threshold voltage
Threshold voltage V = VT, corresponding to the
onset of the strong inversion
Strong inversion occurs when the surface
potential s becomes equal to 2b

In a MOS transistor the


gate voltage is equal to
sum of the potential drops
in the semiconductor and
the oxide

Where F=(KT/q) ln (Na/ni)

Poly gate
We have so far assumed that the Fermi level of
the metal gate was equal to that of the silicon. In
practice this is not the case
In modern devices the gate material is not an
actual metal, but heavily doped polycrystalline
silicon, also called poly silicon
The doping concentration used for that material
is so high (1020/cm3) that it can be considered as
a metal, for all practical purposes.

Work function difference


Energy which is
necessary to extract
an electron with an
energy from the
metal is called the
"work function M
Similarly, the work
function in the
semiconductor is
noted SC

Band diagram for p-n junction

Ec
Efi
EfP
Ev

qVbi = q(n

q p < 0

-xpc

-xp 0

p)

q n > 0

*Na > Nd -> |p| > n

p-type for x<0

n-type for x>0


xn

Ec
EfN
Efi
Ev

xnc

Electron affinity and work function


qc (electron

Eo

affinity)

affinity)

(work function)

Ef

q F

qc (electron

Eo

Ec
Ei
Ev

P type semiconductor

(work function)

Ef

q F

Ec
Ei
Ev

N type semiconductor

MOS capacitor band diagram


If work functions are not same i.e. if metals
work function is smaller than substrate
S = XS + (EC - EF)

Flat band voltage (VFB)


At zero applied voltage, the
bending of the energy bands is
ideally determined by the
difference in the work functions
of the metal and the
semiconductor
This band bending changes
with the applied bias and the
bands become flat when we
apply the so-called flat-band
voltage (VFB)
VFB =(M - S)/q
=(M-XS - EC + EF)/q

MOS-Accumulation region
Charge carriers same as that of substrate type
getting accumulated near Si-SIO2 interface
A MOS structure with a p-type semiconductor
will enter the accumulation regime of operation
when the voltage applied between the metal and
the semiconductor is more negative than the flatband voltage
If VFB is +0.5 V then accumulation region is below
+0.5 V
If VFB is -0.25 V then accumulation region is below
-0.25 V

MOS depletion region


Assume MOS structure with a p-type substrate
When V >VFB, the semiconductoroxide
interface first becomes depleted of holes and we
enter the so-called depletion regime

MOS inversion region


For sufficiently larger voltages than VFB, we
finally arrive at a situation in which the electron
volume concentration at the interface exceeds
the doping density in the semiconductor
This is the strong inversion case in which we
have a significant conducting sheet of inversion
charge at the interface

Charges in the oxide


Oxides grown on silicon contain positive
charges due to the presence of contaminating
metallic ions or imperfect Si-O bonds
These charges can either be fixed or mobile in
the oxide
Mobile ions such as sodium and potassium can
move in the presence of an electric field if the
temperature is high enough

Charges in the oxide


Consider an elementary
positive charge (Q) at a
depth x in the oxide,
where x=0 is now defined
at the metal/oxide
interface
To insure charge
neutrality negative
charges will appear in the
metal and the silicon
The sum of these three
charges is equal to zero

Charges in the oxide


The charge in the
silicon can be removed
if an appropriate
negative voltage is
applied to the gate
If the charge is closer to
the semiconductor a
larger compensation
bias on the gate is
required to remove the
charge in the
semiconductor

Interface traps
Presence of Si-SiO2 interface at the silicon surface
introduces perturbation to the periodic crystal
structure of the semiconductor
Causes some Si-Si bonds to be unfulfilled or "dangling"

As a result there are energy states in the band gap


at the silicon surface
These states are called "interface states" or "interface
traps

They can be charged positively or negatively,


depending on their nature and their energy with
respect to the Fermi level, and thus, will affect the
surface potential
To compensate for these charges, a bias must be
applied to the gate

Flat band voltage-non idealities


Non idealities
Work function difference
Charge in the oxide
Interface states

Threshold voltage
The flat-band voltage must be added to the
expression for the threshold voltage calculated
previously in order to accurately describe the
actual, "non-ideal" threshold voltage

Depletion and enhancement devices


Threshold voltage (VTH) can be either positive or
negative, depending on
Doping concentration (Na)
Material used to form the gate electrode, etc

For a n-channel MOSFET if the threshold


voltage is
negative - depletion-mode device
positive, the device is an enhancement-mode device

Controlling VTH
Depletion-mode devices will have an inversion
layer when the gate voltage is equal to zero
These devices are sometimes referred to as "normally
on".

Enhancement-mode devices require an applied


positive gate voltage to create the inversion
layer
They are sometimes called "normally off"

VTH can be adjusted by introducing a controlled


amount of doping impurities in the channel
region during device fabrication

MOS capacitance
In a MOS capacitor, the metal contact and the
neutral region in the doped semiconductor
substrate are separated by the insulator layer,
the channel, and the depletion region

Capacitance Cmos of the MOS structure can be


represented as a series connection of the
insulator capacitance Ci = Si/di, where S is the
area of the MOS capacitor, and the capacitance
of the active semiconductor layer Cs

Measuring capacitance

low-frequency
ac signal

DC bias

Capacitance in accumulation
When the gate voltage
is negative an
accumulation layer is
present
As the gate voltage
varies a corresponding
OX
variation of the
C
COX Farad / area
tOX
accumulation charge
occurs, and the
Capacitance is
capacitance of the
independent
structure is equal to Cox
of gate voltage

Capacitance in depletion
When the gate voltage is
increased the silicon
surface becomes
depleted, and the
variations of gate voltage
induce variations of the
depletion charge
The value of the
capacitance is then
given by the series
combination of the gate
and depletion region
capacitances

Capacitance decreases
with gate voltage

Capacitance in inversion
As the gate voltage is further increased an
inversion layer is formed and variations of gate
voltage give rise to variations of inversion
charge and thus the measure capacitance is
again equal to COX
OX
C
COX Farad / area
tOX
Capacitance is
independent
of gate voltage

MOS capacitor capacitance as a function


of gate bias

Small-signal equivalent circuit of the MOS


capacitor

Main approximation for compact MOS


modeling: the charge-sheet model
Minority carriers occupy a zero-thickness layer at
the Si-SiO2 interface

(EF-Ei) factor
Positive for n type,
negative for p type
and zero for intrinsic
In other words,
if (EF-Ei) is positive
then in that region we
have more no. of
electrons
if (EF-Ei) is negative
then in that region we
have more no. of holes
If EF=Ei, then no, of
holes = no. of
electrons

Weak inversion and strong inversion


weak inversion:
b < s < 2b
Strong inversion:
s=2b
Flat band condition:
s=0
Accumulation
condition:
s < 0
Depletion:
0 < s < b

Threshold voltage
Consider P type substrate
Suppose you want to invert a region in that
substrate (two step process)
Remove the holes in that region by putting
electrons
No. of holes doping concentration (Ei-EF)

Put some more electrons in that region


How many more electrons doping concentration
(Ei-EF)

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