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IE IC IB
IC IE Ico
IC C IB) ICO
which after some rearrangement gives
ICO
IC
IB
1-
Such that:
ICO
IC IB
1-
IC IB
ic ib
For a practical (non-ideal) transistor this is only
true at a particular bias (operating) point.
IDEAL CE INPUT
Characteristics
The plot is essentially that of a forward biased
diode.
We can thus assume VBE 0.6 V when designing
our d.c. bias circuits.
We can also assume everything we know about
incremental diode resistance when deriving our
a.c. equivalent circuit.
In the non-ideal case IB will vary slightly with
VCE. This need not concern us.
IDEAL CE OUTPUT
(Collector) Characteristics
IDEAL CE OUTPUT
(Collector) Characteristics
Avoid this
saturation
region
where we
try to
forward
bias both
junctions
IDEAL CE OUTPUT
IDEAL CE OUTPUT
(Collector) Characteristics
The plots are all parallel to the VCE axis (i.e.
IC does not depend on VCE)
The curves strictly obey IC = IB
In particular IC = 0 when IB = 0.
We shall work with the ideal characteristic
and later on base our a.c. equivalent circuit
model upon it.
ACTUAL CE OUTPUT
Characteristics
IB =
ACTUAL CE OUPUT
Characteristics
Salient features are:
The finite slope of the plots (IC depends on
VCE)
A limit on the power that can be dissipated.
The curves are not equally spaced (i.e
varies with base current, IB).
ACTUAL CE OUPUT
Characteristics
You will get to measure these curves in the
lab.
There is also a PSPICE sheet DC sweep
analysis and transistor characteristics to
help aid you understanding.