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HW4 Due
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clk
clk
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countmem[0]
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countmem[1]
+1
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clk
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countmem[7]
Unnecessary Calculations
Not synthesizable
Non-static with internal timing control (i.e. @(posedge clk))
Sometimes synthesizable, Sequential logic
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What if n is a parameter?
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end
Use a SM.
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input clk,rst_n;
input [5:0] in;
output [5:0] sum;
RULE OF THUMB:
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condition
State3
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Generated Instantiation
Generate-Loop
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Generate Loop
Generate-Conditional
A generate-conditional allows conditional (pre-synthesis) instantiation
using if-else-if constructs
module multiplier(a ,b ,product);
parameter a_width = 8, b_width = 8;
These are
localparam product_width = a_width+b_width;
parameters,
input [a_width-1:0] a; input [b_width-1:0] b;
not variables!
output [product_width-1:0] product;
generate
if ((a_width < 8) || (b_width < 8))
CLA_multiplier #(a_width,b_width) u1(a, b, product);
else
WALLACE_multiplier #(a_width,b_width) u1(a, b, product);
endgenerate
endmodule
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Generate-Case
A generate-case allows conditional (pre-synthesis) instantiation using case
constructs
See Standard 12.1.3 for more details
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Synthesis Of x And z
in casex
in defaults of conditionals such as :
The else clause of an if statement
The default selection of a case statement
Dont Cares
casex (state)
3b0??: out = 1b1;
3b10?: out = 1b0;
3b11?: out = 1b1;
endcase
state[1:0]
00
01
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state[2]
case (state)
3b001: out = 1b1;
3b100: out = 1b0;
3b110: out = 1b1;
default: out = 1b0;
endcase
case (state)
3b001: out = 1b1;
3b100: out = 1b0;
3b110: out = 1b1;
default: out = 1bx;
endcase
state[1:0]
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01
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state[2]
state[1:0]
state[2]
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Unintentional Latches
Area = 44.02
Either c|d or c&d are passed
through an inverting mux
depending on state of a / b
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Area = 16.08
Does synthesize betterno latch!
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Area = 12.99
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Gated Clocks
clk
clk_en
Min_delay_slack = clk2q THold Skew_Between_clks
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Gated Clocks
Gated clock domains cant be treated lightly:
1.) Skew between domains
2.) Loading of each domain. How much capacitance is on it? What is its
rise/fall times
3,) RC in route. Is it routed in APR like any old signal, or does it have
priority?
2.) Paranoid control freaks (like me) like to generate the gated domains in
custom logic (like clock reset unit). Then let CTS do a balanced distribution
in the APR tool.
Our guest lecturer will cover some of this material.
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Chain Multiplier
module mult(output reg [31:0] out,
input [31:0] a, b, c, d);
always@(*) begin
out = ((a * b) * c) * d;
end
endmodule
Area: 47381
Delay: 8.37
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Tree Multiplier
module multtree(output reg [31:0] out,
input [31:0] a, b, c, d);
always@(*) begin
out = (a * b) * (c * d);
end
endmodule
Area: 47590
Delay: 5.75 vs 8.37
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Area: 15565
Delay: 3.14
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Area:
Delay:
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Loop method
Starts to look
advantageous
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Loop method
Starts to look
advantageous
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Why is it working so
long and hard?
Looking for shared
terms
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Late-Arriving Signals
Circuit reorganization
Rewrite the code to restructure the circuit in a way that minimizes the
delay with respect to the late arriving signal
Logic duplication
This is the classic speed-area trade-off. By duplicating logic, we can
move signal dependencies ahead in the logic chain.
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Exercise
y = a + b + cin;
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Exercise
case(state)
SOME_STATE:
if (late) y = x1;
else y = x2;
default:
if (late) y = x1;
else y = x3;
endcase
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Area = 59.0
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endmodule
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