Design of an Error Detection and

Data Recovery Architecture for

Motion Estimation Testing
Applications
Under the Guidance of
Y.Phani KumarM.Tech,
Assistant Professor, Dept. of ECE,
ASIST,Paritala
by
S.Ratnakar
11AJ1D6813

Abstract:
Motion Estimation in video coding is of most
important concern.
Motion Estimation efficiency can be reduced by the
errors presented in the processing elements.
To effectively estimate the next motion we need to
overcome those errors.

Design For Testability:

We need to test the digital devices before fabrication in

terms of function.
During the early years, design & test were separate
Increased test cost and Decreased test quality lead to
DFT
It has different strategies in those strategies we are using
BIST(Built In Self Test)

Design For Testability:

Its extra logic put in the normal design process flow.
The DFT technique increase the ease of testing .
This technique reduce the system cost.
It guaranteeing the circuit reliability.

Built In Self Test:

It can find the faults and their locations also.
Lower cost of test

Possiblly shorter test times

Tests can be performed throughout the operational life of

the chip
It is extended as BISR and Built In Self Diagnosis.

BIST Architecture:
Test Pattern Generation (TPG)

BIST
Control Unit

Circuitry Under Test

CUT

Test Response Analysis (TRA)

Detailed Architecture of BIST:

Existing Techniques:
Using Residue coding

This can use the residue to detect the errors while

estimating the next motion change in the video
Shift Register

This can use the shift register to estimate next

motion change in video by shifting the values to the
adders.

Proposed Technique:
Due to the drawbacks of the above techniques we are

introducing EDDR technique.

This technique can detect the errors and recover the loosed

data by using the RQ code(Residue Quotient code).

It comprises two major circuit designs,i.e. EDC and DRC
This uses the RQ code i.e., remainder and quotient of the mod

EDDR Architecture:
Primary
Inputs
CUT

TCG

EDC

DRC

S
E
L
E
C
T
O
R

Error free data

or data recovery
results

Detailed architecture of EDDR:

Advantages of Proposed architecture:

More reliability.
Less number of gate counts.

Tools Used:
VHDL

For the verification of circuit design

Xilinx 12.3i

For the synthesis purpose of the proposed design

Applications:
HDTV broadcasting
Live streaming

References:
Design of an Error Detection and Data Recovery Architecture for Motion Estimation
Testing Applications, 2012 IEEE .
Built-in self-detection/correction architecture for motion estimation computing
arrays, IEEE Transaction Very Large Scale Integrated (VLSI) Systems.,vol.55,Feb,
2010.
Testable design and BIST techniques for systolic motion estimators in the transform
domain, in Proc. IEEE International Conference Circuits Systems, Apr. 2009

Built-in self-test design of motion estimation computing array, in Proc. IEEE

Northeast Workshop Circuits Systems, Jun. 2004.

Thank You!!!