Академический Документы
Профессиональный Документы
Культура Документы
rene.beuchat@epfl.ch
rene.beuchat@hesge.ch
Goals
With DE1-SOC
With DE0-nano
3
RB 2006/A2014
Camera
Module
Camera
Ctrl
NIOSII
SRAM
LCD
Ctrl
Display
LCD
Avalon Bus
Slave
JTAG
Master
M/S
FPGA
4
RB 2006/A2014
SDRAM
Ctrl
Memory
SDRAM
LCD specifications
5
RB 2006/A2014
Interface signals:
LCD_ON
Reset_n
CS_n
RS (reg. Sel. C/nD)
Wr_n
Rd_n
D[15..0]
6
RB 2006/A2014
LT24
7
RB 2006/A2014
i2c
8
RB 2006/A2014
9
RB 2006/A2014
10
RB 2006/A2014
11
RB 2006/A2014
CSx :
D/Cx:
WRx:
RDx:
CS_n
D/Cn
WR_n
RD_n
Chip Select
Data / Command_n
Write Access
Read Access
12
RB 2006/A2014
13
RB 2006/A2014
TX07 TFT_LCD
15
RB 2006/A2014
16
RB 2006/A2014
TX07 Synchronization
17
RB 2006/A2014
TX07 Synchronization
18
RB 2006/A2014
TX07
http://www.hitachi-displays-eu.com/doc/TX07D09VM1CAB.pdf
19
RB 2006/A2014
20
RB 2006/A2014
Display
LCD
LCD
Ctrl
SDRAM
Ctrl
NIOSII
Avalon Bus
Addresses
Control
Data
Slave
Master
JTAG
M/S
FPGA
22
RB 2006/A2014
Memory
SDRAM
Epcs
ctrl
Memory
EP16
Name
Function
Reset Val.
Size
0x0
FBAdd
0x1
FBLgt
0x2
DisplayCom
0x3
DisplayStat
0x4
HBP
12
16
0x5
HFP
18
16
0x6
VBP
16
0x7
VFP
20
16
0x8
HData
240
16
0x9
VData
320
16
0xA
HSync
16
0xB
VSync
16
0xC
25
RB 2006/A2014
32
32
Power control
3 signals allows control of Power on the LCD
module. They have to be controlled by the
module as 3 Ports bits.
The DisplayCom register controls them
StepUp_ON :
Allows internal +5V generation, necessary for VGA
and LCD on 45 pins connector
LED_ON :
Allows LED back light ON
LCD_ON :
Needed for LCD TX07 to work
26
RB 2006/A2014
LCD
FIFO
LCD Control
Power
Ctrl
Master Controller
AM_WaitRq
AM_Rd
AM_RData
RB 2006/A2014
AM_BE
Avalon
27
Bus
AM_Add
AS_IRQ
AS_Rd
AS_RData
AS_Wr
AS_WData
AS_Add
AS_CS
Clk
Reset
Registers
29
RB 2006/A2014
M Av
M Av
M Av
M Av
M Av
M Av
RdData
WrData
FIFO_Full
FIFO_Empty
FIFO_Almost_Full
FIFO_Almost_Empty
WrFIFO
Clk
RdFIFO
Clk
35
RB 2006/A2014
FIFO
The Output FIFO_Almost_Empty allows to know if
they are still xx free positions in the FIFO and
FIFO_Almost_Full allows to know if they are already
xx filled positions in the FIFO
xx programmable when FIFO is generated with
MegaWizard
Thus it is possible to know that at least Burst Mode
Size data are available for read access master
transfers to write in FIFO
The size off the FIFO and _Almost_... are defined
at generation time of the FIFO through MegaWizard
36
RB 2006/A2014
FBAdd
0
0
0
Line 0
240 columns
239
0
Line 1
240 columns
FBLgt
239
0
Line 319
240 columns
239
319
37
RB 2006/A2014
239
1 pixel organization:
18 bits/pixel at LCD
Ex. 32 bits /pixel at memory
RGB or BGR ?
38
RB 2006/A2014
1 pixel organization:
18 bits/pixel at LCD
Ex. 16 bits /pixel at memory, 2 pixels / 32 bits
RGB or BGR ?
5-6-5 bits / doublet: RGB, 2 bits lost
39
RB 2006/A2014
Pixel organization
Many choices
Need to be done !
More bits/pixel 18 on 32 bits
more memory for a frame
more bandwidth necessary
more colors available 218 : 262144
Memory space free for other function