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Overview
Basic Concepts
The maximum size of the memory that can be used in any computer is
determined by the addressing scheme.
16-bit addresses = 216 = 64K memory locations
Byte address
Byte address
2 -4
2 -4
2 -3
2- 2
2 - 1
2 - 4
2- 1
2 - 2
2 -3
2 -4
Traditional Architecture
Processor
k-bit
address bus
Memory
MAR
n-bit
data bus
MDR
Up to 2k addressable
locations
Word length =n bits
Control lines
( R / W , MFC, etc.)
Basic Concepts
Semiconductor RAM
Memories
Internal Organization of
Memory Chips
b7
b7
b1
b1
b0
b0
W0
FF
A0
A2
A1
W1
FF
Address
decoder
Memory
cells
A3
W15
Sense / Write
circuit
b1
Sense / Write
circuit
b0
R/W
CS
A Memory Chip
5-bit row
address
W0
W1
5-bit
decoder
32 32
memory cell
array
W31
10-bit
address
Sense/ Write
circuitry
32-to-1
output multiplexer
and
input demultiplexer
5-bit column
address
Data
input/output
R/ W
CS
Static Memories
T1
T2
Word line
Bit lines
Read Operation
In order to read the state of the SRAM cell, the word line is activated to
close switches T1 and T2. If the cell is in state 1, the signal on bit line b is
high and the signal on bit line b is low. The opposite is true if the cell is in
state 0.
Thus, b and b are always complements of each other. The Sense/Write
circuit at the end of the two bit lines monitors their state and sets the
corresponding output accordingly.
Write Operation
During a Write operation, the Sense/Write circuit drives bit lines b and b,
instead of sensing their state.
It places the appropriate value on bit line b and its complement on b and
activates the word line.
This forces the cell into the corresponding state, which the cell retains when
the word line is deactivated.
Vsupply
T3
T4
T1
T2
X
T5
T6
Word line
Bit lines
Static Memories
Figure 5.5. An example of a CMOS memory cell.
Asynchronous DRAMs
Static RAMs are fast, but they cost more area and are more expensive.
Dynamic RAMs (DRAMs) are cheap and area efficient, but they can not
retain their state indefinitely need to be periodically refreshed.
Bit line
Word line
T
C
Row
address
latch
A20 - 9 A 8 -
Row
decoder
4096 (512 8)
cell array
Sense / Write
circuits
Column
address
latch
CA S
CS
R/ W
Column
decoder
D7
D0
Shortly after the row address is loaded, the column address is applied to the
address pins and loaded into the column address latch under control of a
second control line called the ColumnAddress Strobe (CAS).
The information in this latch is decoded and the appropriate group of 8
Sense/Write circuits is selected.
If the R/W control signal indicates a Read operation, the output values of
the selected circuits are transferred to the data lines, D70.
For a Write operation, the information on theD70 lines is transferred to the
selected circuits, then used to overwrite the contents of the selected cells in
the corresponding 8 columns.
In commercial DRAM chips, the RAS and CAS control signals are active
when low.
Hence, addresses are latched when these signals change from high to low.
Synchronous DRAMs
Row
address
latch
Row
decoder
Cell array
Column
address
counter
Column
decoder
Read/Write
circuits & latches
Row/Column
address
Clock
RA S
CA S
R/ W
Mode register
and
timing control
Data input
register
Data output
register
CS
Data
Synchronous DRAMs
Clock
R/ W
RA S
CA S
Address
Data
Row
Col
D0
D1
D2
D3
Synchronous DRAMs
DDR SDRAM
Double-Data-Rate SDRAM
Standard SDRAM performs all actions on the rising
edge of the clock signal.
DDR SDRAM accesses the cell array in the same
way, but transfers the data on both edges of the
clock.
The cell array is organized in two banks. Each can
be accessed separately.
DDR SDRAMs and standard SDRAMs are most
efficiently used in applications where block transfers
are prevalent.
A0
A1
A19
A20
2-bit
decoder
512K 8
memory chip
D31-24
D23-16
D 15-8
D7-0
19-bit
address
8-bit data
input/output
Chip select
Figure 5.10. Organization of a 2M 32 memory module using 512K 8 static memory chips.
Memory System
Considerations
Memory Controller
Row/Column
address
Address
RA S
R/ W
Request
Memory
controller
Processor
CA S
R/ W
CS
Clock
Clock
Data
Memory
Read-Only Memories
Read-Only-Memory
Word line
Flash Memory
Similar to EEPROM
Difference: only possible to write an entire
block of cells instead of a single cell
Low power
Use in portable equipment
Implementation of such modules
Flash cards
Flash drives
Registers
Increasing
size
Primary L1
cache
Increasing Increasing
speed cost per bit
SecondaryL2
cache
Main
memory
Magnetic disk
secondary
memory
Cache Memories
Cache
What is cache?
Why we need it?
Locality of reference (very important)
- temporal
- spatial
Cache block cache line
Cache
Processor
Cache
Replacement algorithm
Hit / miss
Write-through / Write-back
Load through
Main
memory
Main
memory
Block 0
Direct Mapping
tag
tag
tag
Block 1
Cache
Block 127
Block 0
Block 128
Block 1
Block 129
Block 127
Block 255
Block 256
Block 257
Block
Word
Associative Mapping
Main
memory
Block 0
Block 1
Cache
tag
Block 0
tag
Block 1
Block i
tag
Block 127
Block 4095
Tag
Word
12
Main
memory
Block 0
Set-Associative Mapping
Block 1
Cache
tag
Set 0
tag
tag
Set 1
tag
tag
Set 63
tag
Block 0
Block 63
Block 1
Block 64
Block 2
Block 65
Block 3
Block 127
Block 126
Block 128
Block 127
Block 129
Tag
Set
Word
Replacement Algorithms
Performance
Considerations
Overview
Interleaving
ABR
DBR
Module
0
k bits
m bits
Module
Address in module
ABR DBR
Module
i
m bits
k bits
Address in module
Module
MM address
MM address
ABR DBR
ABR DBR
ABR DBR
Module
0
Module
i
Module
k
2 - 1
ABR DBR
Module
n- 1
Other Enhancements
Virtual Memories
Overview
Overview
Address Translation
All programs and data are composed of fixedlength units called pages, each of which
consists of a block of words that occupy
contiguous locations in the main memory.
Page cannot be too small or too large.
The virtual memory mechanism bridges the
size and speed gaps between the main
memory and secondary storage similar to
cache.
Address Translation
Offset
Page frame
Offset
+
PAGE TABLE
Control
bits
Page frame
in memory
Address Translation
TLB
Offset
TLB
Virtual page
number
No
Control
bits
Page frame
in memory
=?
Yes
Miss
Hit
Page frame
Offset
TLB
Memory Management
Requirements
Multiple programs
System space / user space
Protection (supervisor / user state, privileged
instructions)
Shared pages
Secondary Storage
Disk
Disk drive
Disk controller
Sector 3, trackn
Sector 0, track 1
Sector 0, track 0
Sector header
Following the data, there is an errorcorrection code (ECC).
Formatting process
Difference between inner tracks and outer
tracks
Access time seek time / rotational delay
(latency time)
Data buffer/cache
Disk Controller
Processor
Main memory
System bus
Disk controller
Disk drive
Disk drive
Disk Controller
Seek
Read
Write
Error checking
Aluminum
Optical Disks
Pit
Acrylic
Label
Polycarbonate plastic
Land
(a) Cross-section
Pit
Land
Reflection
Reflection
No reflection
Source
Detector
Source
Detector
Source
Detector
0 1 0 0
1 0 0 0 0
1 0 0 0 1
0 0 1 0 0
1 0
Optical Disks
CD-ROM
CD-Recordable (CD-R)
CD-ReWritable (CD-RW)
DVD
DVD-RAM
File
mark
File
mark
File gap
Record
Record
gap
Record
Record
gap
7 or 9
bits