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Experiment
11-0 Introduction to Experiments
11-1 Binary and Decimal Numbers
11-2 Digital Logic Gates
11-3 Simplification of Boolean Functions
11-4 Combinational Circuits
Chapter 11 Laboratory
Experiment
11-5 Code Converters
11-6 Design with Multiplexers
Chapter 11 Laboratory
Experiment
11-10 Counters
11-11 Shift Register
11-12 Serial Addition
11-13 Memory Unit
11-14 Lamp Handball
Chapter 11 Laboratory
Experiment
11-15 Clock Pulse Generator
11-16 Parallel Adder and Accumulator
3. A number of ICs.
Internal circuit
diagram
No connection
Reference Material
Section 1-2 and 1-7
When both R1
and R2 are
equal to 1, all
four cells in the
counter clear to
0 irrespective of
the input pulse.
An inverter
A 2-input AND
A 2-input OR
A 2-input NOR
A 2-input XOR
Note:
If an input to a NAND gate is not used, it should
not be left open, instead, should be connected to
another input that is used.
Reference Material
Section 3-8 and 4-8
Parity Generator:
Design, construct, and test a circuit that
generate an even parity bit from four message
bits. Use XOR gates.
Reference Material
Section 4-3
9's complement
Design a combinational circuit with four input
lines that represent a decimal digit in BCD and
four output lines that generate 9's complement of
the input digit.
The 7447 IC is
a BCD-toseven-segment
decoder/driver.
The 7730
seven-segment
display
contains the
seven LED
segments.
A 47 resistor
to VCC is needed
in order to
supply the
proper current
to the selected
LED segment.
Reference Material
Section 4-10
Mr. X: 2 shares
Mr. Y: 3 shares
Mr. Z: 4 shares
Reference Material
Section 4-3, 4-7 and 4-13
Full Adder
Design, construct, and test a full-adder circuit
using two ICs, 7486 and 7400.
If S=0, A=B
If C4=1, A >= B
If C4=0, A < B
If C4=1 and
S<>0, A >B
11-8 Flip-Flops
Objectives
Construct, test and investigate the operation of
various latches and flip-flops.
Reference Material
Section 5-2 and 5-3
11-8 Flip-Flops
SR Latch
11-8 Flip-Flops
Master-Slave Flip-Flops
11-8 Flip-Flops
Master-Slave Flip-Flops
Observe the waveform of the clock and the master
and slave outputs.
Verify that the delay between the master and the
slave outputs is equal to the positive half of the clock
cycle.
Obtain a timing diagram
11-8 Flip-Flops
Edge-Triggered Flip-Flops
Verify that the
output does not
change when the
clock input is logic-1,
when the clock goes
through a negative
transition, or when it
is logic-0.
11-8 Flip-Flops
Edge-Triggered Flip-Flops
Using a dual-trace
oscilloscope, observe
and record the
timing relationship
between the input
clock and output Q.
11-8 Flip-Flops
IC Flip-Flops
IC type 7476
consists of two JK
master-slave flipflops with preset
and clear.
Investigate the
operation of one
7476 flip-flop and
verify its function
table.
11-8 Flip-Flops
IC Flip-Flops
IC type 7474
consists of two D
positive-edgetriggered flip-flops
with preset and
clear.
Investigate the
operation of the
flip-flop and verify
its function table.
Reference Material
Section 5-7
11-10 Counters
Objectives
Construct and test various ripple and
synchronous counter circuits.
Reference Material
Section 6-3 and 6-4
11-10 Counters
Ripple Counter
Construct a 4-bit binary ripple counter using
two 7476 ICs. Modify the counter so it will
count down instead of up. Check that each
input pulse decrements the counter by 1.
Synchronous Counter
Construct a 4-bit binary counter and check its
operation. Using two 7476 ICs and one 7408
IC.
11-10 Counters
Decimal Counter
Design a synchronous BCD counter that counts
from 0000 to 1001. Using two 7476 ICs and one
7408 IC.
11-10 Counters
Binary Counter With Parallel Load
Two counter-enable
input called P and T.
Both must be equal to 1
for the counter to
operate.
11-10 Counters
Binary Counter With Parallel Load
Reference Material
Section 6-2
Base on
this figure
Reference Material
Section 7-2, 7-3 and 7-5
Memory Expansion
use the CS inputs to select between the two ICs.
Test the circuit by adding a 3-bit number to a 2-bit
number to produce a 4-bit sum.
Reference Material
Section 6-2
Reference Material
Section 10-2
2/3 VCC
1/3 VCC
tH=0.693(RA+RB)C
tL=0.693RBC
Reference Material
Section 10-2
Reference Material
Section 8-6
Reference Material
Section 9-8
Supplement to experiment 2
Compile the circuit described in HDL Example 33 and run the simulator to verify the waveform.