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Addressing Modes of
8086
VARIOUS REGISTERS IN EU
FLAG REGISTER
STATUS FLAGS
CONTROL FLAGS
TF-Single step Trap Flag It is to be set if
single step mode (debugging) is needed.
IF- Interrupt Flag It is to be set, for
allowing or prohibiting interruption
request.
DF- Direction Flag If set, string
instruction automatically decrements the
address (string data transfers proceed
from high address to the low address.
POINTER REGISTER
Two pointer registers are :
Stack pointer The value in the SP
always represents the offset of the next
stack location that can be accessed.
Base pointer It also represents an offset
relative to SS register but is employed in
the based addressing mode of 8086.
8
EU Operation
1. Fetch an instruction from instruction
queue
2. According to the instruction, EU control
logic generates control signals.
(This process is also referred to as instruction
decoding)
AH
BH
CH
DH
SP
BP
SI
DI
AL
BL
CL
DL
ALU
Flag register
General purpose
register
EU
control
instruction
1011000101001010
3-9
MOV AL, BL
Register
mode
Mode
Operand1 Operand2
Operands tell what data should be used in the operation. Operands can
be addresses telling where to get data (or where to store results)
Microprocessor System Design
3-10
INDEX REGISTER
Two index registers are:
Source index (SI)- It is used to store an
offset address for source operand.
Destination index (DI)- It is used for
storage of an offset address for the
destination operand.
11
Memory Segmentation
A segment is a 64KB block of memory starting from any 16-byte
boundary
For example: 00000, 00010, 00020, 20000, 8CE90, and E0840 are all valid
segment addresses
The requirement of starting from 16-byte boundary is due to the 4-bit
left shifting
0
CS
Code Segment
DS
Data Segment
SS
Stack Segment
ES
Extra Segment
3-12
Segment
address
0000
Offset
Memory address
Examples
CS 3 4 8 A 0
4 2 1 4
IP +
Instruction address3 8 A B 4
SS 5 0 0 0 0
F F E 0
SP+
Stack address5 F F E 0
DS 1 2 3 4 0
0 0 2 2
DI +
Data address 1 2 3 6 2
Microprocessor System Design
3-13
Fetching Instructions
Where to fetch the next instruction?
8088
Memory
CS 1 2 3 4
IP
0012
12352
Update IP
After an instruction is fetched, Register IP is updated as follows:
For Example: the length of MOV AL, 0 is 2 bytes. After fetching this instruction
the IP is updated to 0014
Microprocessor System Design
3-14
(assume DS=1234H)
(assume DS=1234H)
(assume SI=0310H)
3-15
ADDRESSING MODES OF
8086
16
AX , BX
Destination
Source
17
Size
Operation
MOV AL, BL
8-bits
Copies BL into AL
MOV CH, CL
8-bits
Copies CL into CH
MOV AX, CX
16-bits
Copies CX into AX
MOV SP, BP
16-bits
Copies BP into SP
MOV BX, ES
16-bits
Copies ES into BX
MOV ECX, EBX
32-bits
Copies EBX into ECX
Both
and the
destination
operands
MOV the
ESP,source
EDX
32-bits
Copies EDX
into ESP
have
been
internal
MOV ES,
DS specified as
the contents
Not allowedof
(segment-to-segment)
registers
of the 8086
MOV BL, DX
Not allowed (mixed sizes)
18
Direct
addressing
differs
from
immediate
addressing, that the locations following the
instruction op-code hold an Offset which is a 16bit offset of the storage location of the operand from
the current value in the data segment (DS) register.
offset is combined with the contents of DS in the
BIU to produce the physical address of the operand.
[DS*10+1000]H
20
AX
[DS*10+[SI]]H
21
MOV AL , [SI+10]
24
25
26