VHDL

Main topics:
■ Circuit design based on VHDL
■ VHDL basics
■ Advanced VHDL language structures
■ Circuit examples

Introduction to VHDL
 Shortly About the VHDL

■ VHDL is an acronym of VHSIC Hardware Description

Language
■ VHSIC is an acronym of Very High Speed Integrated
Circuits
■ A Formal Language for Specifying the Behavior and
Structure of a Digital Circuit
■ Allows Top-Down Design
■ Used to model digital system at many levels of
abstraction( algorithmic level to gate level)
■ Complexity –simple gate to complete digital electronic
system or anything in between.
■ Digital system can be described hierarchically.
■ Timing can also be modeled in the same description.
Introduction to VHDL
 VHDL -INTRODUCTION

■ Vhdl integrated amalgamation of the following languages

--sequential language+
--concurrent language+
--netlist language+
--timing specifications+
--waveform generation language
allows to model the system as interconnection of components.
Defines the syntax ,clear simulation semantics for each language construct.
--model can be verified using VHDL simulator
--strongly typed language.
--sequential language part-ADA pgming language.
--subset sufficient to model most applications
--complete language has sufficient power to capture the description of the
most complex chips to complete electronic system.
Introduction to VHDL
 VHDL Development

■ Initial objective was modeling only and thus only a

simulator was envisaged
■ Subsequently tools for VHDL synthesis were developed

Introduction to VHDL
 HDL Requirements

■ Abstraction
■ Modularity
■ Concurrency
■ Hierarchy

Introduction to VHDL
 Abstraction
VHDL supports description of components as well as systems at various levels of abstraction
■ Gate and component delays
■ Clock cycles
■ Abstract behavior without any notion of delays

Introduction to VHDL
 Modularity

■ Every component in VHDL is referred to as an entity and has a clear interface

■ The interface is called an entity declaration
■ The “internals” of the component are referred to as the architecture declaration
■ There can be multiple architectures at even different levels of abstraction associated with the same
entity

Introduction to VHDL
 constructs

used to express concurrent or sequential behavior of digital

system with or without timing specs.
Test waveforms can be generated
Combination of constructs provides comprehensive
description of the system in a single model.

Introduction to VHDL
 Gajski’s Y-chart
Structural Behavior

Processors, memories Sequential programs

Registers, FUs, MUXs Register transfers

Gates, flip-flops Logic equations/FSM

Each axis represents type of description Transistors Transfer functions
– Behavioral
 Defines outputs as function of inputs Cell Layout
 Algorithms but no implementation Modules
– Structural Chips
 Implements behavior by connecting Boards
components with known behavior Physical
– Physical
 Gives size/locations of components
and wires on chip/board
– Design process is illustrated by travel
route
 VHDL for Simulation & Synthesis

Test Vector Executable Results,

Specification
= Errors
Generator

A Series of
Test
Refined
Vectors
Models
Final Chip
Model
 VHDL for Simulation & Synthesis

VHDL requirements for Simulation

■ Creation of test benches =>
– File I/O
– Detection of errors (function & timing)
– Multiple simultaneous models
– Combination of low & high level models
(for efficiency)
 VHDL for Simulation & Synthesis

VHDL requirements for HW Description

■ Behavioral models =>
– Combinatorial & Sequential Logic
– RTL models
■ Structural models
■ Timing models
 VHDL for Simulation & Synthesis

Requirements for VHDL Synthesis Tools

■ Pre- & post synthesis behavior should be identical
■ Synthesis should be efficient =>
– Requires interaction with place & route tools
– Logic Synthesis
– FSM Synthesis
– Area & Timing Optimization
 New possibilities

■ VHDL frees the designer from having to use von Neumann

structures
– (Neumann János = John von Neumann)
■ It allows him to work with real concurrency instead of
sequential machines
■ This opens up completely new possibilities for the designer
 Reasons for using VHDL

■ Shorter development times for electronic design

■ Simpler maintenance
■ Traditional way: schematic design
 Origin of the VHDL

■ VHDL originated in the early 1980s

– The American Department of Defense initiated the development of
VHDL in the early 1980s
» because the US military needed a standardized method of describing
electronic systems
■ VHDL was standardized in 1987 by the IEEE
■ It is now accepted as one of the most important standard
languages for
– specifying
– verifying
– designing of electronics

Introduction to VHDL
 Standardization 1
■ IEEE standard specification language (IEEE 1076-1993)
for describing digital hardware used by industry worldwide
■ VHDL enables hardware modeling from the gate level to
the system level

■ All the major tool manufacturers now support the VHDL

standard
■ VHDL is now a standardized language, with the advantage
that it is easy to move VHDL code between different
commercial platforms (tools)
=> VHDL code is interchangeable among the different tools
 Standardization 2
■ VHDL is an acronym of VHSIC Hardware Description
Language
■ VHSIC is an acronym of Very High Speed Integrated
Circuits
■ All the major tool manufacturers now support the VHDL
standard
■ VHDL is now a standardized language, with the advantage
that it it easy to move VHDL code between different
commercial platforms (tools)
=> VHDL code is interchangeable among the different tools

Introduction to VHDL
 Standardization 3
■ It was the American Department of Defense which initiated
the development of VHDL in the early 1980s because the US
military needed a standardized method of describing electronic
systems
■ VHDL was standardized in 1987 by the IEEE
– IEEE Std-1076-1987
■ ANSI Standard in 1988
■ Added Support for RTL Design
– VITAL: VHDL Initiative Towards ASIC Library
■ Revised version in 1993
– IEEE Std-1076-1993

Introduction to VHDL
 Standardization 4
■ 1995:
– numeric_std/bit: IEEE-1076.3
– VITAL: IEEE-1076.4
■ 1999: IEEE-1076.1 (VHDL-AMS )
■ 2000:
– IEEE-1076-2000
– IEEE-1076.1-2000 (VITAL-2000, SDF 4.0)
■ Added mixed-signal support to VHDL in 2001 ->
– VHDL-AMS
» IEEE Std-1076.1-2001
■ 2002: IEEE-1076-2002

Introduction to VHDL
 Tools

■ Good VHDL tools, and VHDL simulators in particular,

have also been developed for PCs
■ Prices have fallen dramatically, enabling smaller
companies to use VHDL, too
■ There are also PC synthesis tools, primarily for FPGAs and
EPLDs
 Usage

■ High-tech companies
– Texas Instruments, Intel use VHDL
– most European companies use VHDL
■ Universities
■ VHDL groups to support new users
 IEEE
■ IEEE is the Institute of Electrical and Electronics Engineers
■ The reference manual is called IEEE VHDL Language
Reference Manual Draft Standard version 1076/B
■ It was ratified in December 1987 as IEEE 1076-1987
■ Important:
– the VHDL is standardized for system specification
– but not for design
 Technology independence
■ The design of VHDL components can be technology-independent
or more-or-less technology independent for a technical family
■ The components can be stored in a library for reuse in several
different designs
■ VHDL models of commercial IC standard components can now
be bought, which is a great advantage when it comes to verifying
entire circuit boards
 Analog world
■ VHDL has not yet been standardized for analog electronics
■ Standardization is in progress on VHDL with an analog
extension (AHDL) to allow analog systems to be described
as well
■ This new standard will be based wholly on the VHDL
standard and will have a number of additions for describing
analog functions
 CAPABILITIES OF VHDL
■ Used as exchange medium b/w chip vendors & cad tool users
* different chip vendors can provide vhdl descriptions of their components to
system designers
* CAD Tool users can use it to capture the behavior of the design at high level
of abstraction for functional simulation.

■ Used as communication medium b/w different CAD & CAE Tools

schematic capture may be used to generate a VHDL description for the
design which can be used as i/p to simulation program

■ Supports hierarchy-digital system can be modeled as set of interconnected

components.

■ Supports flexible design methodologies, top down ,bottom up or mixed

■ Not technology specific but is capable of supporting techonology specific

features

Introduction to VHDL
 ■
Supports both synchronous & asynchronous timing models.
■ Modeling techniques such as FSM Descriptions,algorithmic
Descriptions,boolean equations possible
■ Publicly available,human readable ,machine readable not proprietary\
■ IEEE & ANSI standard
■ Supports three basic descriptions styles ie structural,behavioral,dataflow or
combination of these
■ Supports wide range of abstraction levels ranging from abstract behavioral
descriptions to very precise gate level descriptions
■ Design can be captured @ mixed level using single coherent language
■ Arbitrarily large designs can be modeled -- no limitations on the size of the
design
■ Language elements make large scale design modeling easier eg components
,functions ,procedures and packages
■ Test bench can be written using the same language to test vhdl models
■ to VHDL
Introduction
 ■ Nominal ppn delay,min-max delays,set up,hold timing,
timing constraints & spike detection can be described
■ Use of generics & attributes facilitate back
annotation,parameterized designs
■ Model can contain info about the design itself in terms of
user defined attributes such as total area & speed
■ Used to describe library components from different
vendors.
■ Model can be verified by simulation
■ Synthesis description styles are capable of being
synthesized to gate level descriptions
■ Defines new data types
Introduction to VHDL
 VHDL-Related Newsgroups

■ comp.arch.fpga
■ comp.lang.vhdl
■ comp.cad.synthesis

Introduction to VHDL
 Other HDL languages
■ There are several other language extensions built to either aid in RTL construction
or assist in modeling:
– ParaCore - http://www.dilloneng.com/paracore.shtml
– RubyHDL - http://www.aracnet.com/~ptkwt/ruby_stuff/RHDL/index.shtml
– MyHDL - http://jandecaluwe.com/Tools/MyHDL/Overview.shtml
– JHDL - http://www.jhdl.org/
– Lava - http://www.xilinx.com/labs/lava/
– HDLmaker - http://www.polybus.com/hdlmaker/users_guide/
– SystemC
– AHDL – http://www.altera.com
» It is good for Altera-made chips only, which limits its usefulness
» But it is easy to pick up and use successfully
■ The main purpose of a language -- programming, hdl, or otherwise -- is to ease the
expression of design

Introduction to VHDL
 Verilog
■ Verifying Logic
■ Phil Moorby from Gateway Design Automation in 1984 to 1987
– Absorbed by Cadence
» Cadence's ownership of Verilog => others support VHDL
■ Verilog-XL simulator from GDA in 1986
■ Synopsis Synthesis Tool in 1988
■ In 1990 became open language
– OVI: Open Verilog International
■ IEEE Standard in 1995
– IEEE Std-1364-1995
■ Last revision in 2001
– IEEE Std-1364-2001
■ Ongoing work for adding
– Mixed-signal constructs: Verilog-AMS
– System-level constructs: SystemVerilog

Introduction to VHDL
 VHDL vs. Verilog
VHDL Verilog
All abstraction levels All abstraction levels
Complex grammar Easy language
Describe a system (everything) Describe a digital system
Lots of data types Few data types
User-defined package & library No user-defined packages
Full design parameterization Simple parameterization
Easier to handle large designs
Very consistent language. Code written and Less consistent language. If you don't follow
simulated in one simulator will behave exactly some adhoc methodology for coding styles,
the same in another simulator. E.g. strong you will not get it right.
typing rules.

It executes differently on different platforms

unless you follow some adhoc coding rules.

Introduction to VHDL
 VHDL vs. Verilog (Cont.)
■ It does seem that Verilog is easier for designing at the
gate-level, but that people who do higher level simulations express a
preference for VHDL
■ VHDL places constraints on evaluation order that limit the
optimizations that can be performed
– Verilog allows the simulator greater freedom
– For example, multiple levels of zero-delay gates can be collapsed into a single
super-gate evaluation in Verilog
– VHDL requires preserving the original number of delta cycles of delay
in propagating through those levels

VHDL Verilog
In Europe the VHDL is the most popular
language
Based on Pascal language Based on C language
Most FPGA design in VHDL Most ASIC design in Verilog
Introduction to VHDL
 VHDL vs. Verilog: Process block
■ VHDL:
process (siga, sigb)
begin
…...
end;
■ Verilog:
always @ (siga or sigb)
begin
….
end

Introduction to VHDL
 VHDL vs. Verilog:
Concurrent Signal Assignment

■ VHDL:
c <= a and b;
■ Verilog:
assign c = a & b ;

Introduction to VHDL
 VHDL vs. Verilog: Signal Delays
■ VHDL:
a <= transport b after 1 ns;
■ Verilog:
#1 assign a = b;
» ‘a’ output is delayed by 1 time unit
» The ‘# ‘ operator is the delay operator
» # N will delay for N simulation units
» Delays can assigned to both inputs and outputs
#1 assign a = #1 b;
» ‘b’ is delayed by 1 unit, then assigned to ‘a’, which is then delayed by 1 time
unit

Introduction to VHDL
 VHDL vs. Verilog: Clock Generator
■ VHDL:
signal clk : std_logic := ‘0’;
process
begin
clk <= not (clk) after clkperiod/2;
wait on clk;
end;
■ Verilog:
initial clk = 0;
always #(clkperiod/2) clk = ~ clk;

Introduction to VHDL
 Verilog Weakness
■ Not well suited for complex, high level modeling
– No user defined type definition
– No concept of libraries, packages, configurations
– No ‘generate’ statement - can’t build parameterized structural models
– No complex types above a two-dimensional array

Introduction to VHDL
 VHDL vs. Verilog:
Managing Large designs

■ VHDL:
– Configuration, generate, generic and package statements all help manage
large design structures
■ Verilog:
– There are no statements in Verilog that help manage large designs

Introduction to VHDL
 VHDL vs. Verilog:
Procedures and Tasks

■ VHDL:
– allows concurrent procedure calls

■ Verilog:
– does not allow concurrent task calls

Introduction to VHDL
 VHDL vs. Verilog:
Structural Replication

■ VHDL:
– The generate statement replicates a number of instances
of the same design-unit or some sub part of a design, and
connects it appropriately

■ Verilog:
– There is no equivalent to the generate statement in
Verilog.

Introduction to VHDL
 Languages “under development”
■ SystemVerilog
– Extending Verilog to higher levels of abstraction for architectural and
algorithm design and advanced verification
■ VHDL 200x
– Goal of VHDL Analysis and Standards Group (VASG):
» Enhance/update VHDL for to improve performance, modeling capability,
ease of use, simulation control, and the type system
■ e.g.: Data types and abstractions:

– variant records
– interfaces

Introduction to VHDL
 VHDL Example

■ And gate

a
AND c
b

Introduction to VHDL
 VHDL Description: AND gate
entity AND2 is
port (a, b: in bit ;
c : out bit);
end AND2;

architecture beh of AND2 is

begin
c <= a and b;
end beh;

Introduction to VHDL
 Concurrency in VHDL Descriptions

signals signals

process 1 process 2 process n

Introduction to VHDL
 Concurrent and Sequential Computations
■ Processes are concurrent
■ Sequential activity within each process

Introduction to VHDL
 Hierarchy in VHDL
C 0

C 1 C 2 C 3

C 4 C 5 C 6 C 7 S 1 1

S 1 2
S 1 S 3 S 6 S 7

S 2 S 4 S 8

S 9
S 1 3
S 1 0
S 1 4

S 5

Introduction to VHDL
 Modeling Styles in VHDL

Introduction to VHDL
 Modeling Styles
■ Semantic model of VHDL

■ Structural description

■ Data Flow description

■ Algorithmic description

■ RTL description

Introduction to VHDL
 Modeling Choices in VHDL
■ Behavioral and Structural Domains
– Several Levels of Abstraction
■ Multiple Styles of Behavioral Description:
– Data Flow Style (concurrent)
– Procedural Style (sequential)
■ Combinations, variations and special cases of these, e.g.,
– special case of data flow style - FSM described using guarded blocks
– special case of procedural style - FSM described using case statement in a
process

Introduction to VHDL
 Structural Description

■ Carries same information as a NET LIST

■ Net List = (Component instances) + (Nets)
■ Structural Description in VHDL =
(Signals) + (Component instances + Port maps)
■ Many sophisticated features in VHDL to make it more versatile:
* Variety of signal types
* Generic components
* Generate statements for creating arrays of component instances
* Flexibility in binding components to design entities and architectures

Introduction to VHDL
 Behavioral Description
■ Procedural ■ Non-procedural
(textual order => execution order) (textual order NOT => execution order)
■ Sequential statements ■ Concurrent statements
■ Control constructs alter normal sequential ■ Data flow (or rather data dependency
flow restricts concurrency)

Called Behavioral description in VHDL Called Data flow description in VHDL

Introduction to VHDL
 Concurrent Statements in VHDL

■ process statement -- behavior

■ concurrent procedure call -- behavior
■ concurrent signal assign. -- data flow
■ component instantiation -- structure
■ generate statement -- structure
■ block statement -- nesting
■ concurrent assertion stmt -- error check

Introduction to VHDL
 Example: 1-bit Full Adder

entity FullAdder is
port (X, Y, Cin: in bit; -- Inputs
Cout, Sum: out bit); -- Outputs
end FullAdder;

X Sum
Y FullAdder
Cin Cout

Introduction to VHDL
 Example: 1-bit Full Adder (contd.)

Architecture Equations of FullAdder is

begin -- Concurrent Assignment
Sum <= X xor Y xor Cin after 10 ns;
Cout <= (X and Y) or (X and Cin) or (Y and Cin) after 5ns;
end Equations;

Introduction to VHDL
 Example: 4-bit Adder
entity Adder4 is
port (A, B: in bit_vector(3 downto 0);
Ci: in bit; -- Inputs
S: out bit_vector(3 downto 0);
Co: out bit); -- Outputs
end Adder4;

Introduction to VHDL
 Example: 4-bit Adder (contd.)

Architecture Structure of Adder4 is

Component FullAdder
port (X, Y, Cin: in bit; Cout, Sum: out bit);
signal C: bit_vector (3 downto 1);
begin -- Instantiations
FA0: FullAdder port map (A(0), B(0), Ci, C(1), S(0));
FA1: FullAdder port map (A(1), B(1), C(1), C(2), S(1));
FA2: FullAdder port map (A(2), B(2), C(2), C(3), S(2));
FA3: FullAdder port map (A(3), B(3), C(3), Co, S(3));
end Structure;

Introduction to VHDL
 Example: 4-bit Comparator

entity nibble_comparator is
port (a, b: in bit_vector (3 downto 0);
gt,eq,lt : in bit;
a_gt_b, a_eq_b, a_lt_b : out bit);
end nibble_comparator;

Introduction to VHDL
 Structural Description (contd.)
architecture iterative of nibble_comparator is
component comp1
port (a, b, gt,eq,lt : in bit; a_gt_b, a_eq_b, a_lt_b : out bit);
end component;
for all : comp1 use entity work.bit_comparator(gate_level);
signal im: bit_vector (0 to 8);
begin
c0:comp1 port map(a(0),b(0), gt, eq, lt, im(0), im(1), im(2));
c1toc2: for i in 1 to 2 generate
c:comp1 port map(a(i),b(i),im(i*3-3),im(i*3-2),im(i*3-1),
im(i*3+0),im(i*3+1),im(i*3+2));
end generate;
c3: comp1 port map(a(3),b(3),im(6),im(7),im(8),
a_gt_b, a_eq_b, a_lt_b);
end nibble_comparator;

Introduction to VHDL
 Example: 1-bit Comparator
(data flow)
entity comp1 is
port (a, b, gt,eq,lt : in bit; a_gt_b, a_eq_b, a_lt_b : out bit);
end comp1;
architecture dataflow of comp1 is
signal s : bit;
begin
s <= (a and b) or (not a and not b);
a_gt_b <= (gt and s) or (a and not b);
a_lt_b <= (lt and s) or (not a and b);
a_eq_b <= eq and s;
end dataflow;

Introduction to VHDL
 ■ Behavioral Description in VHDL

Introduction to VHDL
 Modeling Styles
■ Semantic model of VHDL

■ Structural description

■ Data Flow description

■ Algorithmic description

■ RTL description

Introduction to VHDL
 Concurrent Statements in VHDL

■ process statement -- behavior

■ concurrent procedure call -- behavior
■ concurrent signal assign. -- data flow
■ component instantiation -- structure
■ generate statement -- structure
■ block statement -- nesting
■ concurrent assertion stmt -- error check

Introduction to VHDL
 Example: D Flip-Flop

entity DFF is
port (D, CLK: in bit;
Q: out bit; QN: out bit := ‘1’) ;
end DFF;

D Q
DFF
CLK QN

Introduction to VHDL
 Example: DFF (contd.)
Architecture Beh of DFF is
begin process (CLK)
begin if (CLK = ‘1’ then
Q <= D after 10 ns;
QN <= not D after 10 ns;
endif;
endprocess;
end Beh;

Introduction to VHDL
 Concurrent Conditional Assignment:
4 to 1 Multiplexer
y <= x0 when sel = 0
else x1 when sel = 1
else x2 when sel = 2
else x3 when sel = 3

x0
x1 y
x2
x3
sel
Introduction to VHDL
 CASE Statement:
4 to 1 Multiplexer
Case sel is
when 0 => y <= x0
when 1 => y <= x1 x0
when 2 => y <= x2 x1 y
x2
when 3 => y <= x3 x3
end case

Introduction to VHDL
 VHDL Processes
General form of Process
process(sensitivity-list)
begin
sequential-statements
end process;
Process example
process (B, C, D)
begin
A <= B; -- statement 1
B <= C; -- statement 2
C <= D; -- statement 3
end process;

Introduction to VHDL
Introduction to VHDL