REVERSIBLE COMPUTING

PERFORMANCE ANALYSIS
Presented by
Shiny M.I(13003)
Priyadharshini.M(14006)
Sree Ranjani R(14008)

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Outline
Overview about the reversible logic
gates.
Types of reversible logic gates.
To design a combinational circuit
using reversible logic gates.
To design a sequential circuit using
reversible logic gates.
Simulation using Hspice.
Application of reversible logic gates.
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Introduction
A circuit is reversible if it maps each
input vector into a unique output
vector and vice versa.
Reversible Gates are circuits in which
number of outputs is equal to the
number of inputs and there is a one
to one correspondence between the
vector of inputs and outputs.
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Some reversible gates..

Feynman Gate
Double Feynman
Gate (F2G)
Toffoli Gate
Fredkin Gate
Peres Gate
Double Peres gate
NCG[Nines
compliment gate]
SBV Gate
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BSCL gate
MKG Gate
SCL Gate
DPG Gate
BME Gate
DKG Gate
BVF Gate
TKS Gate
TSG Gate
URG Gate
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Feynman Gate
The input vector is I (A, B) and the
output vector is O(P, Q).
The outputs are defined by P=A,
Q=A xor B.

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Double Feynman Gate

(F2G)
The input vector is I (A, B, C) and the
output vector is O(P, Q, R).
The outputs are defined by P = A,
Q=A xor B, R=A xor C.

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Fredkin Gate
The input vector is I (A, B, C) and the
output vector is O(P, Q, R).
The output is defined by P=A, Q= A
B xor AC and R= A C xor AB

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Toffoli Gate
The input vector is I(A, B, C) and the
output vector is O(P,Q,R).
The outputs are defined by P=A,
Q=B, R=AB xor C.

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Peres Gate
The input vector is I (A, B, C) and the
output vector is O (P, Q, R).
The output is defined by P = A, Q = A
xor B and R=AB xor C.

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Double Peres gate

The input vector is I(A,B,C,D) and the
output vector is O(P,Q,R,S).
The output is defined by P=A,Q=A
xor B,
R=A xor B xor D and S=(A xor B)D xor
AB xor C.

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DKG Gate

A 4* 4 reversible DKG gate that can

work singly as a reversible Full adder
and a reversible Full subtractor.
If input A=0, the proposed gate
works as a reversible Full adder, and
if input A=1, then it works as a
reversible Full subtractor.

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DKG GATE

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Goals of reversible logic

synthesis
1. Minimize the garbage
2. Minimize the width of the circuit
(the number of additional inputs)
3. Minimize the total number of gates
4. Minimize the delay

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COMBINATIONAL CIRCUIT

Combinational logic is a type of digital logic, which is

implemented by Boolean circuit.
The output of the combinational logic is a pure function of
the present input .
Combinational logic is used incomputercircuits to
performBoolean algebra on input signals , some are
* Half adders, Full adders, Half subtractions, Full
subtractions.
*Multiplexer, De-multiplexers
* Encoders and Decoders

FULL ADDER

MULTIPLEXER
A multiplexer can use addressing bits to select one of
several input bits to be the output.
* A selector chooses a single data input and
passes it to the MUX output
* It has one output selected at a time.

CONVENTIONAL 4 TO 1 MULTIPLEXER
Consists of:
Inputs (multiple) = 2n
Output (single)
Selectors (depends on the inputs) = n
Enable (active high or active low)

REVERSIBLE LOGIC
Double Peres gate
The input vector is I(A,B,C,D) and the output vector is O(P,Q,R,S).
The full adder circuit is implemented using DPG gate

SEQUENTIAL CIRCUITS
Sequential circuits use current input variables and previous
input variables by storing the information and feedback the
output into the circuit in the next clock cycle.
The memory elements are used to store the past history,
*Wire
* Latches and
* Flip flops.

D FLIP FLOP

The D flip flop tracks the input, making transitions with match those of the
input D.
The D stands for "data, this flip flop stores the value that is on the data
line

REVERSIBLE LOGIC

The gate is one through, which means one of the input variables is also
output.
The proposed reversible RR gate is parity preserving. This is
verified by comparing the input parity ABCD to the
output parity PQRS.
The D Flip flop is designed using RR reversible logic ,with a feedback
part.

MASTER SLAVE D FLIPFLOP

The master stage is positive level sensitive, while the slave stage is
negative level sensitive.
When the clock is high, the master stage follows the D input
while the slave stage holds the previous value.
When the clock changes from logic 1to logic 0, the master
latch ceases to sample the input and stores the D value at
the time of the clock transition and the slave passes the
stored master value to the output.

Performance of Reversible
Gate
(A) Peres gate: PG(A, B, C) = A B C
(B) Fredkin gate: F(A, B, C) = AB + AC or
F(A, B, C) = AC + AB
(C) Toffoli gate (4 inputs, 4 outputs):
TG4(A, B, C, D) = A B C D
(D) Feynman gate: FG(A, B) = A B
(E) NOT gate: NOT(A) = A
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DKG Reversible Gate

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DKG used for Full Adder

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Conventional Full Adder

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Reversible DKG gate-Full Adder

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Area-Conventional Full Adder

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Area DKG Reversible Gate FA

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Power-Conventional Full Adder

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power DKG Reversible Gate FA

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D-FlipFlop

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Fredkin Gate

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Fayman Gate

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Application of Reversible logic gates

Low power CMOS.
Quantum computer.
Nanotechnology .
Optical computing .
Design of low power arithmetic and data
path for digital signal processing (DSP).
Field Programmable Gate Arrays (FPGAs)
in CMOS technology for extremely low
power, high testability and self-repair .

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CONCLUSION
Reversible Computing is an attractive research
area.
The reversible circuits form the basic building
block of quantum computers as all quantum
operations are reversible.
It also better for designing computational
blocks to overcome the garbage outputs and
complexity of gates.
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References
1.Thapliyal H, M.B.Shrinivas. A New Reversible TSG Gate and Its
Application for Designing Efficient Adder Circuits. Centre for VLSI and
Embedded System Technologies International Institute of Information
Technology, Hyderabad, 500019, India.
2. Himanshu Thapliyal and M.B Srinivas, A beginning in the reversible
logic synthesis of sequential circuits having features of online
testability, SPIE Microelectronics, MEMS, and Nanotechnology
Symposium, Brisbane, Australia, December 11-14, 2005.
3. R. Feynman, Quantum Mechanical Computers, Optical News,
1985, pp. 11-20
4. Raghava Garipelly1, P.Madhu Kiran2, A.Santhosh Kumar3 A Review
on Reversible Logic Gates and their ImplementationInternational
Journal of Emerging Technology and Advanced Engineering . Volume 3,
Issue 3, March 2013
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Thank You

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