LOGO

TRNG I HC BCH KHOA H NI

VIN IN T VIN THNG

Introduction

IC Design Lab

LOGO

Contents
1. Introduction

2. Design Project

3. Simulation

4. Synthesize the design

LOGO

1. Introduction
Modelsim

Quartus

LOGO

1. Introduction
1.1 Modelsim

ModelSim is a verification and simulation tool for

VHDL, Verilog, SystemVerilog, and mixed-language
designs.
Software : ModelSim-Altera 6.6d Starter Edition
References :
Introduction to Simulation of Verilog Designs Using ModelSim Graphical Waveform
Editor (Altera).
ModelSim Tutorial (Mentor Graphics).
http://www.altera.com

LOGO

1. Introduction
1.2 Quartus
Quartus .
Software : Quartus II 11.1 Web Edition
References :
Quartus Tutorial .
http://www.altera.com

LOGO

Contents
1. Introduction

2. Design Project

3. Simulation

4. Synthesize the design

LOGO

2. Design Project
Simple example : f(x1, x2, x3) = x1x2 + x2x3 + x3x1

Verilog code :

module majority(x1, x2 ,x3 ,f);

input x1, x2, x3;
output f;
assign f = (x1&x2)|(x2&x3)|(x3&x1);
endmodule;

LOGO

2. Design Project
Open the ModelSim simulator. In the displayed window
select File > New > Project

LOGO

2. Design Project
A Create Project pop-up box will appear
1.Enter the name of
the project

Choose Project
Location

LOGO

2. Design Project
Create new file

2
3

LOGO

2. Design Project

Double click

Text Editor

LOGO

2. Design Project
Or add existing file

LOGO

2. Design Project
After completed coding, select Compile > Compile all

Compile of majority.v was successfull

LOGO

Contents
1. Introduction

2. Design Project

3. Simulation

4. Synthesize the design

LOGO

3. Simulation
3.1. Simulate without testbench
3.2. Simulate with testbench

LOGO

3. Simulation
3.1. Simulate without testbench
Select Simulate > Start simulation, Start Simulation
window will appear

LOGO

3. Simulation
Simulation window

LOGO

3. Simulation
Create waveforms for Simulation

LOGO

3. Simulation
Modify waveforms for Simulation

LOGO

3. Simulation
Waveform window

LOGO

3. Simulation
Waveform window

LOGO

3. Simulation
With output signal

LOGO

3. Simulation
SimulateSelect Run all

LOGO

3. Simulation
Result

To stop simulation, slect Simulate -> End simulation

LOGO

3. Simulation
3.2. Simulate with testbench
Create testbench file to project

LOGO

3. Simulation
After completed coding, select Compile > Compile all

LOGO

3. Simulation
Add signal to waveform

LOGO

3. Simulation
Add signal to waveform

LOGO

3. Simulation
Simulate

LOGO

3. Simulation
Zoom in, zoom out

LOGO

Contents
1. Introduction

2. Design Project

3. Simulation

4. Synthesize the design

LOGO

4. Synthesize the design

Open the Quartus . In the displayed window select File
> New Project Wizard

LOGO

4. Synthesize the design

A New Project Wizard box will appear
1. Directory
2 . Name

www.themegallery.com

LOGO

4. Synthesize the design

Family & Device Settings will appear

LOGO

4. Synthesize the design

LOGO

4. Synthesize the design

Entity will appear

LOGO

4. Synthesize the design

Text editor code

Ctrl + S save

LOGO

4. Synthesize the design

Or add file

LOGO

4. Synthesize the design

After coding, select Processing > Start Complation

LOGO

4. Synthesize the design

RTL viewer select Tool > Netlist Viewers > RTL
Viewer

LOGO

4. Synthesize the design

Assign select Assignments > Pin Planner

Build

LOGO

4. Synthesize the design

After Assign, select Toll > Programmer

LOGO

LOGO

Thank You !