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TRNG I HC BCH KHOA H NI


VIN IN T VIN THNG

Introduction

IC Design Lab

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Contents
1. Introduction

2. Design Project

3. Simulation

4. Synthesize the design

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1. Introduction
Modelsim

Quartus

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1. Introduction
1.1 Modelsim

ModelSim is a verification and simulation tool for


VHDL, Verilog, SystemVerilog, and mixed-language
designs.
Software : ModelSim-Altera 6.6d Starter Edition
References :
Introduction to Simulation of Verilog Designs Using ModelSim Graphical Waveform
Editor (Altera).
ModelSim Tutorial (Mentor Graphics).
http://www.altera.com

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1. Introduction
1.2 Quartus
Quartus .
Software : Quartus II 11.1 Web Edition
References :
Quartus Tutorial .
http://www.altera.com

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Contents
1. Introduction

2. Design Project

3. Simulation

4. Synthesize the design

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2. Design Project
Simple example : f(x1, x2, x3) = x1x2 + x2x3 + x3x1

Verilog code :

module majority(x1, x2 ,x3 ,f);


input x1, x2, x3;
output f;
assign f = (x1&x2)|(x2&x3)|(x3&x1);
endmodule;

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2. Design Project
Open the ModelSim simulator. In the displayed window
select File > New > Project

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2. Design Project
A Create Project pop-up box will appear
1.Enter the name of
the project

Choose Project
Location

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2. Design Project
Create new file

2
3

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2. Design Project

Double click

Text Editor

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2. Design Project
Or add existing file

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2. Design Project
After completed coding, select Compile > Compile all

Compile of majority.v was successfull

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Contents
1. Introduction

2. Design Project

3. Simulation

4. Synthesize the design

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3. Simulation
3.1. Simulate without testbench
3.2. Simulate with testbench

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3. Simulation
3.1. Simulate without testbench
Select Simulate > Start simulation, Start Simulation
window will appear

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3. Simulation
Simulation window

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3. Simulation
Create waveforms for Simulation

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3. Simulation
Modify waveforms for Simulation

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3. Simulation
Waveform window

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3. Simulation
Waveform window

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3. Simulation
With output signal

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3. Simulation
SimulateSelect Run all

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3. Simulation
Result

To stop simulation, slect Simulate -> End simulation

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3. Simulation
3.2. Simulate with testbench
Create testbench file to project

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3. Simulation
After completed coding, select Compile > Compile all

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3. Simulation
Add signal to waveform

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3. Simulation
Add signal to waveform

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3. Simulation
Simulate

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3. Simulation
Zoom in, zoom out

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Contents
1. Introduction

2. Design Project

3. Simulation

4. Synthesize the design

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4. Synthesize the design


Open the Quartus . In the displayed window select File
> New Project Wizard

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4. Synthesize the design


A New Project Wizard box will appear
1. Directory
2 . Name

www.themegallery.com

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4. Synthesize the design


Family & Device Settings will appear

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4. Synthesize the design

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4. Synthesize the design


Entity will appear

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4. Synthesize the design


Text editor code

Ctrl + S save

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4. Synthesize the design


Or add file

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4. Synthesize the design


After coding, select Processing > Start Complation

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4. Synthesize the design


RTL viewer select Tool > Netlist Viewers > RTL
Viewer

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4. Synthesize the design


Assign select Assignments > Pin Planner

Build

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4. Synthesize the design


After Assign, select Toll > Programmer

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Thank You !