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Chapter 3 :: Sequential Logic Design

Digital Design and Computer Architecture


David Money Harris and Sarah L. Harris

Copyright 2007

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Chapter 3 :: Topics

Introduction
Latches and Flip-Flops
Synchronous Logic Design
Finite State Machines
Timing of Sequential Logic
Parallelism

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Introduction
Outputs of sequential logic depend on current and
prior input values it has memory.
Some definitions:
State: all the information about a circuit necessary to
explain its future behavior
Latches and flip-flops: state elements that store one bit
of state
Synchronous sequential circuits: combinational logic
followed by a bank of flip-flops

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Sequential Circuits

Give sequence to events


Have memory (short-term)
Use feedback from output to input to store
information

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State Elements

The state of a circuit influences its future


behavior
State elements store state

Bistable circuit
SR Latch
D Latch
D Flip-flop

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Bistable Circuit
Fundamental building block of other state elements
Two outputs: Q, Q
No inputs

I2

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I1

I1

I2

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Bistable Circuit Analysis


Consider the two possible cases:
Q = 0: then Q = 1 and Q = 0 (consistent)

1
0

Q = 1: then Q = 0 and Q = 1 (consistent)


0
1

I1

I2

I1

I2

Bistable circuit stores 1 bit of state in the state variable, Q (or


Q)
But there are no inputs to control the state
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SR (Set/Reset) Latch
SR Latch

N1

N2

Consider the four possible cases:

S = 1, R = 0
S = 0, R = 1
S = 0, R = 0
S = 1, R = 1

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SR Latch Analysis
S = 1, R = 0: then Q = 1 and Q = 0

S = 0, R = 1: then Q = 0 and Q = 1
R

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N1

N2

N1

N2

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SR Latch Analysis
S = 1, R = 0: then Q = 1 and Q = 0

0
N1

S = 0, R = 1: then Q = 0 and Q = 1
R

0
1

N2

1
N1

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0
0

N2

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SR Latch Analysis
S = 0, R = 0: then Q = Qprev
Qprev = 0
R

N1

Qprev = 1

N2

N1

N2

S = 1, R = 1: then Q = 0 and Q = 0
R

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N1

N2

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SR Latch Analysis
S = 0, R = 0: then Q = Qprev and Q = Qprev (memory!)
Qprev = 0
R

Qprev = 1
0

N1

0
0

N1

0
1

N2

1
0

N2

S = 1, R = 1: then Q = 0 and Q = 0 (invalid state: Q NOT Q)


R

1
N1

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0
1

N2

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SR Latch Symbol
SR stands for Set/Reset Latch
Stores one bit of state (Q)

Control what value is being stored with S, R inputs


Set: Make the output 1 (S = 1, R = 0, Q = 1)
Reset: Make the output 0 (S = 0, R = 1, Q = 0)

Must do something to avoid


invalid state (when S = R = 1)

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SR Latch
Symbol
R

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D Latch
Two inputs: CLK, D
CLK: controls when the output changes
D (the data input): controls what the output changes to

Function
When CLK = 1, D passes through to Q (the latch is transparent)
When CLK = 0, Q holds its previous value (the latch is opaque)

Avoids invalid case when Q NOT Q

D Latch
Symbol
CLK
D

Q
Q

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D Latch Internal Circuit


CLK

CLK D
0
X
1
0
1
1

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R
S

CLK

Q Q

Q Q

Q
Q

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D Latch Internal Circuit


CLK

CLK D
0
X
1
0
1
1

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D
X
1
0

R
S

Q Q
Q Q

S
0
0
1

R
0
1
0

CLK
D

Q
Q

Q
Q
Qprev Qprev
0
1
1
0

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D Flip-Flop
Two inputs: CLK, D
Function
The flip-flop samples D on the rising edge of CLK
When CLK rises from 0 to 1, D passes through to Q
Otherwise, Q holds its previous value

Q changes only on the rising edge of CLK

A flip-flop is called an edge-triggered device because it is


activated on the clock edge
D Flip-Flop
Symbols
D

Q
Q

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D Flip-Flop Internal Circuit


Two back-to-back latches (L1 and L2) controlled by
complementary clocks
When CLK = 0
L1 is transparent
L2 is opaque
D passes through to N1

When CLK = 1
L2 is transparent
L1 is opaque
N1 passes through to Q

CLK
CLK
D D
L1

Q
Q

N1

CLK
D

Q Q

L2

Q Q

Thus, on the edge of the clock (when CLK rises from 0 1)


D passes through to Q

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D Flip-Flop vs. D Latch


CLK
D

Q
Q

Q
Q

CLK
D
Q (latch)
Q (flop)

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D Flip-Flop vs. D Latch


CLK
D

Q
Q

Q
Q

CLK
D
Q (latch)
Q (flop)

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Registers
CLK

D0

D1

Q0

CLK

Q1

D3:0
D2

Q2

D3

Q3

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Q3:0

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Enabled Flip-Flops
Inputs: CLK, D, EN
The enable input (EN) controls when new data (D) is stored

Function
EN = 1
D passes through to Q on the clock edge

EN = 0

Internal
Circuit

the flip-flop retains its previous state

EN
0
D

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Symbol

CLK

Q
EN

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Resettable Flip-Flops
Inputs: CLK, D, Reset
Function:
Reset = 1
Q is forced to 0

Reset = 0
the flip-flop behaves like an ordinary D flip-flop

Symbols

Reset

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Resettable Flip-Flops
Two types:
Synchronous: resets at the clock edge only
Asynchronous: resets immediately when Reset = 1

Asynchronously resettable flip-flop requires changing the


internal circuitry of the flip-flop (see Exercise 3.10)
Synchronously resettable flip-flop?

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Resettable Flip-Flops
Two types:
Synchronous: resets at the clock edge only
Asynchronous: resets immediately when Reset = 1

Asynchronously resettable flip-flop requires changing the


internal circuitry of the flip-flop (see Exercise 3.10)
Synchronously resettable flip-flop?
Internal
Circuit
CLK
D
Reset

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Settable Flip-Flops
Inputs: CLK, D, Set
Funtion:
Set = 1
Q is set to 1

Set = 0
the flip-flop behaves like an ordinary D flip-flop

Symbols

Set

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Sequential Logic
Sequential circuits: all circuits that arent combinational
A problematic circuit:
X

X
Y
Z
0 1 2 3 4 5 6 7 8 time (ns)

This circuit has no inputs and 1-3 outputs

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Sequential Logic
Sequential circuits: all circuits that arent combinational
A problematic circuit:
X

Y
Z
0 1 2 3 4 5 6 7 8 time (ns)

This circuit has no inputs and 1-3 outputs


It is an astable circuit that oscillates
Its period depends on the delay of the inverters which
depends on the manufacturing process, temperature, etc
The circuit has a cyclic path: output fed back to input
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Synchronous Sequential Logic Design


Breaks cyclic paths by inserting registers
These registers contain the state of the system
The state changes at the clock edge, so we say the system is
synchronized to the clock
Rules of synchronous sequential circuit composition:

Every circuit element is either a register or a combinational circuit


At least one circuit element is a register
All registers receive the same clock signal
Every cyclic path contains at least one register

Two common synchronous sequential circuits


Finite State Machines (FSMs)
Pipelines

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Finite State Machine (FSM)


Consists of:
State register that
Store the current state and
Load the next state at the clock edge

Combinational logic that


Computes the next state
Computes the outputs

CLK
S
Next
State

S
Current
State

Next State
Logic

CL

Next
State

Output
Logic

CL
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Outputs

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Finite State Machines (FSMs)


Next state is determined by the current state and the inputs
Two types of finite state machines differ in the output logic:
Moore FSM: outputs depend only on the current state
Mealy FSM: outputs depend on the current state and the inputs
Moore FSM

inputs

next
state
logic

CLK
next
k state
k

state

output
logic

outputs

Mealy FSM

inputs

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next
state
logic

CLK
next
k state
k state

output
logic

outputs

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Finite State Machine Example


Traffic light controller

Bravado

Traffic sensors: TA, TB (TRUE when theres traffic)


Lights: LA, LB
Dining
Hall

LA

Academic
Labs

TB

TA

LA
TA

TB

Blvd.

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LB

LB

Ave.
Dorms

Fields

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FSM Black Box


Inputs: CLK, Reset, TA, TB
Outputs: LA, LB
CLK

TA
TB

Traffic
Light
Controller

LA
LB

Reset

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FSM State Transition Diagram


Moore FSM: outputs labeled in each state
States: Circles
Reset
Transitions: Arcs
S0
LA: green
LB: red

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FSM State Transition Diagram


Moore FSM: outputs labeled in each state
States: Circles
TA
Reset
Transitions: Arcs
TA
S0
LA: green
LB: red

S1
LA: yellow
LB: red

S3
LA: red
LB: yellow

S2
LA: red
LB: green

TB
TB

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FSM State Transition Table


Current
State

Next
State

Inputs

TA

TB

S0

S0

S1

S2

S2

S3

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S'

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FSM State Transition Table


Current
State

Next
State

Inputs

TA

TB

S'

S0

S1

S0

S0

S1

S2

S2

S3

S2

S2

S3

S0

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FSM Encoded State Transition Table


Current State

Inputs

Next State

S1

S0

TA

TB

S'1

S'0

State

Encoding

S0

00

S1

01

S2

10

S3

11

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FSM Encoded State Transition Table


Current State

Inputs

Next State

S1

S0

TA

TB

S'1

S'0

State

Encoding

S0

00

S1

01

S2

10

S3

11

S'1 = S1 S0
S'0 = S1S0TA + S1S0TB
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FSM Output Table


Current State

Outputs
LA1

S0

green

00

yellow

01

red

10

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LA0

LB1

LB0

Output Encoding

S1

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FSM Output Table


Current State

Outputs
Output Encoding

S1

S0

LA1

LA0

LB1

LB0

green

00

yellow

01

red

10

LA1 = S1
LA0 = S1S0
LB1 = S1
LB0 = S1S0
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FSM Schematic: State Register


CLK
S'1

S1

S'0

S0
r
Reset

state register

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FSM Schematic: Next State Logic


CLK

TA

S'1

S1

S'0

S0
r

TB

Reset
S1

inputs

S0
next state logic

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state register

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FSM Schematic: Output Logic


CLK
S'1

LA1
S1
LA0

TA

S'0

S0

LB1

r
TB

Reset
S1

inputs

S0

LB0
next state logic

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state register

output logic

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outputs

FSM Timing Diagram


Cycle 1

Cycle 2

Cycle 3

Cycle 4

Cycle 5

Cycle 6

Cycle 7

Cycle 8

Cycle 9

Cycle 10

CLK
Reset
TA
TB
S'1:0

??

S1:0

??

S0 (00)

S1

LA1:0

??

Green (00)

Yellow (01)

LB1:0

??

Red (10)

S0 (00)

S1 (01)

S2

S3

(10)

(01)

(11)

S2 (10)

S3 (11)

Red (10)

15

20

25

30

S1
S0 (00)

Yellow (01) Red (10)

35

40

45

TA

Reset
S0
LA: green
LB: red

S3
LA: red
LB: yellow

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TA

S1
LA: yellow
LB: red

S2
LA: red
LB: green

TB
TB

(01)

Green (00)

Green (00)

10

S0 (00)

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t (sec)

FSM State Encoding


Binary encoding: i.e., for four states, 00, 01, 10, 11
One-hot encoding

One state bit per state


Only one state bit is HIGH at once
I.e., for four states, 0001, 0010, 0100, 1000
Requires more flip-flops
Often next state and output logic is simpler

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Moore vs. Mealy FSM


Alyssa P. Hacker has a snail that crawls down a paper tape
with 1s and 0s on it. The snail smiles whenever the last four
digits it has crawled over are 1101. Design Moore and Mealy
FSMs of the snails brain.

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State Transition Diagrams


Moore FSM
reset

S0
0

S1
0

S2
0

S3
0

S4
1
0

Mealy FSM: arcs indicate input/output

Mealy FSM
reset

1/1
1/0

S0

1/0
S1

0/0

0/0
S2

1/0

S3
0/0

0/0

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Moore FSM State Transition Table


Current State Inputs Next State
S2

S1

S0

State

Encoding

S0

000

S1

001

S2

010

S3

011

S4

100

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S'2

S'1

S'0

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Moore FSM State Transition Table


Current State Inputs Next State
S2

S1

S0

S'2

S'1

S'0

State

Encoding

S0

000

S1

001

S2

010

S3

011

S4

100

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Moore FSM Output Table

Current State

Output

S2

S1

S0

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Moore FSM Output Table

Current State

Output

S2

S1

S0

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Y = S2

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Mealy FSM State Transition and Output Table

Current State

Input

Next State

S1

S0

State

Encoding

S0

00

S1

01

S2

10

S3

11

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S'1

S'0

Output
Y

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Mealy FSM State Transition and Output Table

Current State

Input

Next State

Output

S1

S0

S'1

S'0

State

Encoding

S0

00

S1

01

S2

10

S3

11

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Moore FSM Schematic


A

CLK
S'2

S2

S'1

S1

S'0

S0

Reset

S2

S1

S0

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Mealy FSM Schematic


A
CLK
S'1

S1

S'0

S0

Reset

S1

S0

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Moore and Mealy Timing Diagram

Cycle 1

Cycle 2

Cycle 3

Cycle 4

Cycle 5

Cycle 6

Cycle 7

Cycle 8

Cycle 9 Cycle 10

CLK
Reset
A

Moore Machine
S

??

S0

S1

S2

S2

S3

S4

S2

S3

S4

S0

S1

S2

S3

S1

S0

Mealy Machine
S

??

S0

S1

S2

S2

S3

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Factoring State Machines


Break complex FSMs into smaller interacting
FSMs
Example: Modify the traffic light controller to
have a Parade Mode.
The FSM receives two more inputs: P, R
When P = 1, it enters Parade Mode and the Bravado
Blvd. light stays green.
When R = 1, it leaves Parade Mode

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Parade FSM
Unfactored FSM

P
R

Controller
FSM

TA
TB

LA
LB

Factored FSM
P
R

Mode
FSM
M

TA
TB

Lights
FSM

LA
LB

Controller
FSM

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Unfactored FSM State Transition Diagram


P TA
P TA

R TA

Reset
P TA

S0
LA: green
LB: red

S1
LA: yellow
LB: red

R TA

R TA

S4
LA: green
LB: red

P TA

S5
LA: yellow
LB: red
R

P
S3
LA: red
LB: yellow

R TA

P TB
P TB

S2
LA: red
LB: green

R
S7
LA: red
LB: yellow

S6
LA: red
LB: green
R
R TB

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R TB

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Factored FSM State Transition Diagram

TA

Reset
S0
LA: green
LB: red

TA

S1
LA: yellow
LB: red

Reset
S3
LA: red
LB: yellow

S2
LA: red
LB: green

MTB

S0
M: 0

S1
M: 1

M + TB
Lights FSM

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R
Mode FSM

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FSM Design Procedure

Identify the inputs and outputs


Sketch a state transition diagram
Write a state transition table
Select state encodings
For a Moore machine:

For a Mealy machine:

Rewrite the state transition table with the selected state encodings
Write the output table
Rewrite the combined state transition and output table with the selected
state encodings

Write Boolean equations for the next state and output logic
Sketch the circuit schematic

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Timing

Flip-flop samples D at clock edge


D must be stable when it is sampled
Similar to a photograph, D must be stable around the clock
edge
If D is changing when it is sampled, metastability can occur

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Input Timing Constraints


Setup time: tsetup = time before the clock edge that data must
be stable (i.e. not changing)
Hold time: thold = time after the clock edge that data must be
stable
Aperture time: ta = time around clock edge that data must be
stable (ta = tsetup + thold)
CLK

D
tsetup thold

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ta

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Output Timing Constraints


Propagation delay: tpcq = time after clock edge that the output
Q is guaranteed to be stable (i.e., to stop changing)
Contamination delay: tccq = time after clock edge that Q might
be unstable (i.e., start changing)
CLK
Q
tccq
tpcq

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Dynamic Discipline
The input to a synchronous sequential circuit must be stable
during the aperture (setup and hold) time around the clock
edge.
Specifically, the input must be stable
at least tsetup before the clock edge
at least until thold after the clock edge

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Dynamic Discipline
The delay between registers has a minimum and
maximum delay, dependent on the delays of the circuit
elements
CLK

CLK
Q1

(a)

CL

R1

D2
R2

Tc
CLK
Q1
D2
(b)

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Setup Time Constraint


The setup time constraint depends on the maximum delay from
register R1 through the combinational logic.
The input to register R2 must be stable at least tsetup before the clock
edge.
CLK

CLK
Q1

CL

D2

R1

R2
Tc

Tc

CLK
Q1
D2
tpcq

tpd

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tsetup

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Setup Time Constraint


The setup time constraint depends on the maximum delay from
register R1 through the combinational logic.
The input to register R2 must be stable at least tsetup before the clock
edge.
CLK

CLK
Q1

CL

D2

R1

R2
Tc

Tc tpcq + tpd + tsetup


tpd

CLK
Q1
D2
tpcq

tpd

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tsetup

3-<69>

Setup Time Constraint


The setup time constraint depends on the maximum delay from
register R1 through the combinational logic.
The input to register R2 must be stable at least tsetup before the clock
edge.
CLK

CLK
Q1

CL

D2

R1

R2
Tc

Tc tpcq + tpd + tsetup


tpd Tc (tpcq + tsetup)

CLK
Q1
D2
tpcq

tpd

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tsetup

3-<70>

Hold Time Constraint


The hold time constraint depends on the minimum delay from
register R1 through the combinational logic.
The input to register R2 must be stable for at least thold after the clock
edge.
CLK

CLK

Q1
R1

CL

D2
R2

thold <

CLK
Q1
D2
tccq tcd
thold

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3-<71>

Hold Time Constraint


The hold time constraint depends on the minimum delay from
register R1 through the combinational logic.
The input to register R2 must be stable for at least thold after the clock
edge.
CLK

CLK

Q1
R1

CL

D2
R2

thold < tccq + tcd


tcd >

CLK
Q1
D2
tccq tcd
thold

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3-<72>

Hold Time Constraint


The hold time constraint depends on the minimum delay from
register R1 through the combinational logic.
The input to register R2 must be stable for at least thold after the clock
edge.
CLK

CLK

Q1
R1

CL

D2
R2

thold < tccq + tcd


tcd > thold - tccq

CLK
Q1
D2
tccq tcd
thold

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3-<73>

Timing Analysis
CLK

CLK

Timing Characteristics

tccq = 30 ps

tpcq = 50 ps

tpd =

X'

thold = 70 ps
Y'

per gate

tsetup = 60 ps

tpd = 35 ps
tcd = 25 ps

tcd =
Setup time constraint:

Hold time constraint:

Tc

tccq + tpd > thold ?

fc = 1/Tc =

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3-<74>

Timing Analysis
CLK

CLK

Timing Characteristics

tccq = 30 ps

tpcq = 50 ps

X'

thold = 70 ps
Y'

tpd = 3 x 35 ps = 105 ps

per gate

tsetup = 60 ps

tpd = 35 ps
tcd = 25 ps

tcd = 25 ps
Setup time constraint:

Hold time constraint:

Tc (50 + 105 + 60) ps = 215 ps

tccq + tpd > thold ?

fc = 1/Tc = 4.65 GHz

(30 + 25) ps > 70 ps ? No!

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3-<75>

Fixing Hold Time Violation


Timing Characteristics

Add buffers to the short paths:


CLK

CLK

tccq = 30 ps

tpcq = 50 ps

tsetup = 60 ps

tpd =

X'

Y'

thold = 70 ps
per gate

tpd = 35 ps
tcd = 25 ps

tcd =
Setup time constraint:

Hold time constraint:

Tc

tccq + tpd > thold ?

fc =

Copyright 2007

3-<76>

Fixing Hold Time Violation


Timing Characteristics

Add buffers to the short paths:


CLK

CLK

tccq = 30 ps

tpcq = 50 ps

tsetup = 60 ps

X'

Y'

tpd = 3 x 35 ps = 105 ps

thold = 70 ps
per gate

tpd = 35 ps
tcd = 25 ps

tcd = 2 x 25 ps = 50 ps
Setup time constraint:

Hold time constraint:

Tc (50 + 105 + 60) ps = 215 ps

tccq + tpd > thold ?

fc = 1/Tc = 4.65 GHz

(30 + 50) ps > 70 ps ? Yes!

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3-<77>

Clock Skew
The clock doesnt arrive at all registers at the same time
Skew is the difference between two clock edges
Examine the worst case to guarantee that the dynamic discipline is
not violated for any register many registers in a system!

delay

CLK

CLK1

CLK2
Q1

R1

C
L

D2
R2

t skew

CLK1
CLK2
CLK

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3-<78>

Setup Time Constraint with Clock Skew


In the worst case, the CLK2 is earlier than CLK1
CLK1

CLK2
Q1

C
L

R1

Tc

D2
R2

CLK1

Tc

CLK2
Q1
D2
tpcq

tpd

Copyright 2007

tsetup tskew

3-<79>

Setup Time Constraint with Clock Skew


In the worst case, the CLK2 is earlier than CLK1
CLK1

CLK2
Q1

C
L

R1

Tc

D2
R2

CLK1

Tc tpcq + tpd + tsetup + tskew

CLK2

tpd

Q1
D2
tpcq

tpd

Copyright 2007

tsetup tskew

3-<80>

Setup Time Constraint with Clock Skew


In the worst case, the CLK2 is earlier than CLK1
CLK1

CLK2
Q1

C
L

R1

Tc

D2
R2

CLK1

Tc tpcq + tpd + tsetup + tskew

CLK2

tpd Tc (tpcq + tsetup + tskew)

Q1
D2
tpcq

tpd

Copyright 2007

tsetup tskew

3-<81>

Hold Time Constraint with Clock Skew


In the worst case, CLK2 is later than CLK1
CLK1

CLK2
Q1

R1
CLK1

CL

D2
R2

tccq + tcd >

CLK2

tcd >

Q1
D2
tccq tcd
tskew thold

Copyright 2007

3-<82>

Hold Time Constraint with Clock Skew


In the worst case, CLK2 is later than CLK1
CLK1

CLK2
Q1

R1
CLK1

CL

D2
R2

tccq + tcd > thold + tskew

CLK2

tcd >

Q1
D2
tccq tcd
tskew thold

Copyright 2007

3-<83>

Hold Time Constraint with Clock Skew


In the worst case, CLK2 is later than CLK1
CLK1

CLK2
Q1

R1
CLK1

CL

D2
R2

tccq + tcd > thold + tskew

CLK2

tcd > thold + tskew tccq

Q1
D2
tccq tcd
tskew thold

Copyright 2007

3-<84>

Violating the Dynamic Discipline


Asynchronous (for example, user) inputs might violate the dynamic
discipline
tsetup thold

taperture

CLK
Q

Case I

D
Q

Case II

D
Q
D

Copyright 2007

???

Case III

button

CLK

3-<85>

Metastability
Any bistable device has two stable states and a metastable state
between them
A flip-flop has two stable states (1 and 0) and one metastable state
If a flip-flop lands in the metastable state, it could stay there for an
undetermined amount of time

metastable
stable

Copyright 2007

stable

3-<86>

Flip-flop Internals
Because the flip-flop has feedback, if Q is somewhere between 1
and 0, the cross-coupled gates will eventually drive the output to
either rail (1 or 0, depending on which one it is closer to).
R

N1

N2

A signal is considered metastable if it hasnt resolved to 1 or 0


If a flip-flop input changes at a random time, the probability that the
output Q is metastable after waiting some time, t, is:
P(tres > t) = (T0/Tc ) e-t/
tres

: time to resolve to 1 or 0
T0, : properties of the circuit

Copyright 2007

3-<87>

Metastability
Intuitively:
T0/Tc describes the probability that the input changes at a bad
time, i.e., during the aperture time
P(tres > t) = (T0/Tc ) e-t/
is a time constant indicating how fast the flip-flop moves away
from the metastable state; it is related to the delay through the
cross-coupled gates in the flip-flop
P(tres > t) = (T0/Tc ) e-t/

In short, if a flip-flop samples a metastable input, if you


wait long enough (t), the output will have resolved to 1
or 0 with high probability.
Copyright 2007

3-<88>

Synchronizers
Asynchronous inputs (D) are inevitable (user interfaces,
systems with different clocks interacting, etc.).
The goal of a synchronizer is to make the probability of
failure (the output Q still being metastable) low.
A synchronizer cannot make the probability of failure 0.
CLK

Copyright 2007

SYNC

3-<89>

Synchronizer Internals

A synchronizer can be built with two back-to-back flip-flops.


Suppose the input D is transitioning when it is sampled by flip-flop
1, F1.
The amount of time the internal signal D2 can resolve to a 1 or 0 is
CLK
CLK
(Tc - tsetup).
D2

F1

F2
Tc

CLK
D2

metastable

Copyright 2007

tres

tsetup

tpcq

3-<90>

Synchronizer Probability of Failure


For each sample, the probability of failure of this synchronizer is:

P(failure) = (T0/Tc ) e-(Tc - tsetup)/


CLK

CLK
D2

F1

F2
Tc

CLK
D2

metastable

Copyright 2007

tres

tsetup

tpcq

3-<91>

Synchronizer Mean Time Before Failure

If the asynchronous input changes once per second, the probability of


failure per second of the synchronizer is simply P(failure).
In general, if the input changes N times per second, the probability of
failure per second of the synchronizer is:

P(failure)/second = (NT0/Tc) e-(Tc - tsetup)/

Thus, the synchronizer fails, on average, 1/[P(failure)/second]


This is called the mean time between failures, MTBF:

MTBF = 1/[P(failure)/second] = (Tc/NT0) e(Tc - tsetup)/

Copyright 2007

3-<92>

Example Synchronizer
CLK

CLK
D2

D
F1

Suppose:
T0

Tc

= 1/500 MHz = 2 ns

Q
F2

= 200 ps

= 150 ps tsetup = 100 ps

N = 10 events per second


What is the probability of failure? MTBF?
P(failure) =
P(failure)/second =
MTBF

Copyright 2007

3-<93>

Example Synchronizer
CLK

CLK
D2

D
F1

Suppose:
T0

Tc

= 1/500 MHz = 2 ns

Q
F2

= 200 ps

= 150 ps tsetup = 100 ps

N = 1 events per second


What is the probability of failure? MTBF?
P(failure) = (150 ps/2 ns) e-(1.9 ns)/200 ps
= 5.6 10-6
P(failure)/second = 10 (5.6 10-6 )
= 5.6 10-5 / second
MTBF = 1/[P(failure)/second] 5 hours

Copyright 2007

3-<94>

Parallelism
Two types of parallelism:
Spatial parallelism
duplicate hardware performs multiple tasks at once

Temporal parallelism
task is broken into multiple stages
also called pipelining
for example, an assembly line

Copyright 2007

3-<95>

Parallelism Definitions
Some definitions:
Token: A group of inputs processed to produce a group of outputs
Latency: Time for one token to pass from start to end
Throughput: The number of tokens that can be produced per unit time

Parallelism increases throughput.

Copyright 2007

3-<96>

Parallelism Example
Ben Bitdiddle is baking cookies to celebrate the installation of
his traffic light controller. It takes 5 minutes to roll the cookies
and 15 minutes to bake them. After finishing one batch he
immediately starts the next batch. What is the latency and
throughput if Ben doesnt use parallelism?
Latency =
Throughput =

Copyright 2007

3-<97>

Parallelism Example
Ben Bitdiddle is baking cookies to celebrate the installation of
his traffic light controller. It takes 5 minutes to roll the cookies
and 15 minutes to bake them. After finishing one batch he
immediately starts the next batch. What is the latency and
throughput if Ben doesnt use parallelism?
Latency = 5 + 15 = 20 minutes = 1/3 hour
Throughput = 1 tray/ 1/3 hour = 3 trays/hour

Copyright 2007

3-<98>

Parallelism Example
What is the latency and throughput if Ben uses parallelism?
Spatial parallelism: Ben asks Allysa P. Hacker to help, using her own
oven
Temporal parallelism: Ben breaks the task into two stages: roll and
baking. He uses two trays. While the first batch is baking he rolls the
second batch, and so on.

Copyright 2007

3-<99>

Spatial Parallelism
Latency:
time to
first tray

Spatial
Parallelism

10

15

Tray 1

Ben 1

Ben 1

Tray 2

Alyssa 1

Alyssa 1

20

25

30

35

40

45

50

Time
Roll

Tray 3

Ben 2

Ben 2

Tray 4

Alyssa 2

Alyssa 2

Bake
Legend

Latency =
Throughput =

Copyright 2007

3-<100>

Spatial Parallelism
Latency:
time to
first tray

Spatial
Parallelism

10

15

Tray 1

Ben 1

Ben 1

Tray 2

Alyssa 1

Alyssa 1

20

25

30

35

40

45

50

Time
Roll

Tray 3

Ben 2

Ben 2

Tray 4

Alyssa 2

Alyssa 2

Bake
Legend

Latency = 5 + 15 = 20 minutes = 1/3 hour


Throughput = 2 trays/ 1/3 hour = 6 trays/hour

Copyright 2007

3-<101>

Temporal Parallelism
Latency:
time to
first tray
0

10

15

20

25

30

35

40

45

50

Temporal
Parallelism

Time
Tray 1

Ben 1

Tray 2

Ben 1
Ben 2

Tray 3

Ben 2
Ben 3

Ben 3

Latency =
Throughput =

Copyright 2007

3-<102>

Temporal Parallelism
Latency:
time to
first tray
0

10

15

20

25

30

35

40

45

50

Temporal
Parallelism

Time
Tray 1
Tray 2

Ben 1

Ben 1
Ben 2

Tray 3

Ben 2
Ben 3

Ben 3

Latency = 5 + 15 = 20 minutes = 1/3 hour


Throughput = 1 trays/ 1/4 hour = 4 trays/hour
Using both techniques, the throughput would be 8 trays/hour

Copyright 2007

3-<103>