STATIC UPS FAILURESORIGIN AND POSSIBLE

PREVENTION

Sanjay B.R
1 M.Tech
SJEC

CONTENTS
Introduction
Event
Probable

Cause
Proposed Corrective Action
Conceptual Design
Analysis
Conclusion
References

1. Introduction :
Static

inverters are used by various industrial

and institutional facilities as uninterruptable
power supplies (UPS), providing a reliable source
of AC power to critical loads.

In

some applications, loads supplied by UPS

inverters can tolerate occasional failures, but
others, such as critical buses at nuclear power
plants, are much more sensitive to a loss of
these units.

In

many cases, an UPS failure at a nuclear power

plant will result in a partial or total failure of
reactor protection systems.

 This

paper presents preliminary investigation

of UPS failures at a nuclear power plant.

An

analysis of the failure along with the results

of diagnostic testing.

The

corrective actions were proposed to

eliminate effects of transients on the UPS
thyristor bridge.

The

discussion also includes the design and

evaluation of a proposed change in the circuit
that will prevent inadvertent thyristor misfiring
while leaving the proper operation of the
bridge unaffected.

Arrangemen
t:

 The

two UPS inverters used throughout this

discussion are 35KVA units and will be identified as
UPS-1 and UPS-2.
Both UPS units are identical (one primary and one
back-up).
Each unit connected to a common 600-volt AC bus, a
common 125-volt DC battery bank, and a common
load bus.
Under normal operation one UPS is supplying 120
volt AC power to the load bus while the other is
energized and in a stand-by mode of operation.
The load is alternated between both UPS units every
three months.
Also connected to the load bus, through a static
transfer switch, is a 120-volt bypass AC supply.
Should the AC output of the UPS inverter approach
zero volts, the load bus will automatically transfer to
the bypass supply within one quarter cycle.

 Each

UPS rectifies a 3 phase 600 volt AC source to

approximately 140 volts DC.
This DC power is then applied to a thyristor bridge
where it is converted to a 60-Hertz square wave.
This 60-Hertz square wave is then passed through a
tuned ferro-resonant filter, producing a 60-Hertz,
120-volt sine wave output.
Should the 600-volt AC power source become
unavailable to the rectifier section of the UPS, a
battery bank is available to replace the DC power to
the thyristor bridge and maintain the square wave
output.
Located at the DC input to the thyristor bridge
inverter and the load side of both the rectified DC
and the battery bank, an 800 amp semi-conductor
fuse (identified as F2) is used to protect the power
electronic components (diodes, thyristors, etc.) from
damage due to high short circuit currents.

2. Event :
With

UPS-1 operating normally, the F2 fuse

actuated due to a short circuit condition in the
inverter bridge.
The fuse actuation resulted in a loss of DC
power to the invertor bridge.
With the loss of the DC power to the inverter,
the sinusoidal AC output degraded to a point
where the UPS loads transferred to a bypass
AC supply, which was still available.
Due to the momentary degradation in the AC
output, several components on the UPS AC
load bus became de-energized.
This resulted in the initiation of about half of
the reactor trip system.
With the situation stabilized, the load bus was
transferred to UPS-2, which was in the stand-

 With

UPS-1 de-energized, the unit was inspected

for any obvious damage and testing was performed
in an attempt to find any short circuit conditions.
Nothing abnormal was , found.
Following recommendations made by the
manufacturer of the UPS units, the power electronic
component of the bridge circuit (inverter diodes,
thyristors, and commutating capacitors) were
tested by re-energizing the unit.
The F2 fuse was then replaced and the unit was
successfully energized.
It was concluded that the power components were
not defective and did not cause the fuse to actuate.
Preliminary testing and inspection did not reveal
any physical faults within the unit.
The focus of the investigation was then directed at
thyristor mis-firing and possible cause.

 Two

control boards located within the machine

determine the firing angles of the thyristors.
Each of the two control boards was replaced on
both UPS1 and UPS-2 and sent to the
manufacturer for further evaluation.
The AC load bus, which had been transferred to
UPS-2, was transferred back to UPS-1 in order to
take temperature readings within the machine.
After the UPS-1 had been supplying the AC load
bus for some time, ambient temperature
reading were taken within the UPS and found to
be approximately 1000 F.
This temperature was within the rating of the
machine.

 Two

months later, the F2 fuse again actuated, but

this time with UPS-2 supplying the AC load.
Since new control boards had been recently
installed on this unit, defective control boards
were ruled out as a probable cause.
The manufacturer, who could find no problems
with any of the original control boards during
their testing reinforced this conclusion.
After the malfunction on UPS-2 additional testing
and data gathering activities were initiated.
Total harmonic distortion (THD) readings on both
units were collected and were found to be within
acceptable limits.
A review of the station data recorders was
performed and revealed that no abnormal
conditions existed within the power plant at the
time the F2 fuse actuated.

technician provided by the manufacturer

arrived on site and began performing diagnostic
testing in order to identify the problem.
He proceeded to obtain various inverter input
and output waveforms.
The DC ripple at the input of the inverter bridge
was satisfactory.
The square wave output of the bridge along with
the sine wave output of the ferro-resonant filter
also were within specifications.
The pulse signals produced by the gate signal
circuit board to the main inverter bridge
thyristors were examined and were found to be
acceptable.
The technician performed a de-energized
inspection of each UPS and no problems could be
found.

3. Probable Cause :
Since

inspections and testing could not identify

any defective part(s) in either machine, it was
determined that the F2 fuse actuation was not
caused by faulty machine components.
Since both machines share a common AC and
DC bus, it was concluded that a transient on
either bus could affect the firing control circuit
boards resulting in the misfiring of the thyristors.
Another factor which supported this conclusion
was the fact that two additional UPS units which
also share AC and DC busses (isolated from the
busses shared by UPS-1 and 2) had not had any
F2 fuse actuations or any other operational
problems.

4. Proposed Corrective Action :

As

previously stated, a detailed examination of

plant conditions surrounding the F2 fuse
actuations did not reveal anything abnormal.
However, the data collection equipment used
at the plant can only record events of long
duration, typically several cycles in duration.
The manufacturer stated that transients as
short as one-half cycle in duration could result
in the misfire of the thyristors.
It is possible that a transient on the main AC or
DC busses may have been introduced into the
thyristor control circuits and not been detected.
In order to determine the origin and nature of
the transients, extensive upgrades would have
to be installed on existing recording equipment.

 The

benefits of such an upgrade would not justify

the very large capital expenditure.
Even if the source of the transients could be
discovered, there would be no guarantee that the
problem could be eliminated.
Therefore, this was not considered a viable option.
Because of the non-destructive nature of the
transients, it was decided that the corrective
action should focus on eliminating the effects of
the transients and not eliminating the transients
themselves.
From this point, the corrective action
concentrated on designing a circuit that would
greatly reduce the probability that a transient in
the supply system would cause a short circuit in
the inverter bridge circuit.

5. Conceptual Design :

 The

design will use a sensing circuit to detect

when the thyristors of the inverter bridge are
conducting or not.

The

output of the sensing circuits will then be

used to control the gate pulse to the
thyristors.

The

concept behind the design is to allow gate

pulses to reach the gates of one pair of
thyristors only after the alternate pair has
stopped conducting.

The

controlling devices will be MOSFET

transistors placed in series with each of the

 These

transistors will act as on/off switches

for the gate pulses and will pass the gate
signal when its corresponding sensing circuit
allows.

For

the sake of this discussion, the transistors

will be labeled TCI, TC2, TC3, and TC4.

The

inverter bridge thyristors will be

identified as T1, T2, T3, and T4 with TI and
T4 conducting as a pair and T2 and T3
conducting as the alternate pair.

 The

sensing circuits (fig.2) will be made up of a

voltage-divider network.

This

network will consist of a fixed value

resistor in series with a variable resistor.

Since

the DC voltage in the UPS can vary, the

variable resistor is needed to adjust the voltage
drop across the resistors to a maximum 5 volts.

The

network will be connected across each of

the four thyristors.

 When

a particular thyristor is conducting it will,

in effect, provide a short circuit path around
the resistor network resulting in a voltage drop
across the resistors of approximately 0 volts.

When

the thyristors are not conducting, The

short circuit now becomes an open circuit and
a voltage drop develops across the network.

The

overall effect of this sensing circuit is to

provide a 5-volt signal when the thyristors are
off and a 0-volt signal when the thyristors are
on.

digital logic circuit (fig.3) will be used to

process the voltage signals from the sensing
networks.

The

logic circuits will consist of-six AND gates.

single AND gate, identified as Al, A2, A3,

or A4, will be connected to each of the four
sensing circuits.

The

outputs of this first logic level will be

connected to a second level of logic, which
consists of 2 AND gates, identified as C1 and
C2.

The

outputs of A1 and A4 will be connected

 The

outputs of C1 and C2 will be used to

control the gate pulses to the thyristors by
allowing the MOSFETs in the thyristor gate
circuits to either conduct or turn off.

C1

will be connected to the gate leads of TC2

and TC3 while C2 will be connected to TC1
and TC4.

The

desired result of this control circuit is to

block any signal to the non-conducting pair of
thyristors in the bridge circuit while the other
pair is still conducting.

Assuming

that thyristors T1 and T4 are

conducting, the inputs to AI and A4 will be

zero input to C1 places approximately 0-volts to

the gate leads of TC2 and TC3.

As

long as TC2 and TC3 are not conducting any

inadvertent pulse from the firing control circuits of
T2 and T3 cannot reach the thyristors.

This

ensures that T2 and T3 will not conduct as long

as T1 and T4 are conducting.

Once

the forced commutation circuit turns off TI and

T4, AI and A4 will produce a logic 1 at their outputs.
This output will produce a corresponding logic 1
output at Cl.
This logic 1 output will turn on TC2 and TC3, allowing
the gate pulse from the firing circuit to reach
thyristors T2 and T3.

6.
Analysis :
Voltage Divider Network :
The

resistance values for the voltage divider

networks used for the sensing circuit have been
chosen to be between 1OO K and 105 K.
The network will also have negligible effects on
the forced commutation circuit.
The resistances of the voltage divider network
must be closely matched to avoid developing an
appreciable voltage across the load impedance.
The 0-5 K variable resistors must be adjusted
to develop the proper voltage levels needed to
pulse the AND gates and to null out, any
unwanted voltages across the load.

Time Delays :
Because of the circuitry of the gate control circuit,
there will be some time delay from the time the
gate signal circuit boards initiate the turn on
signal to the instant that the MOSFETs allow this
signal to reach the thyristors.
The

total time delay before the switching circuit will

allow a gate pulse to pass to the thyristors was
determined using typical values for AND gates and
MOSFETs.

The

total time delay was calculated as 18.4ns for

the two AND gates and the MOSFET.
Since a typical turn on time for a power thyristor is
20s, the minimum time duration of the main gate
pulse from the circuit boards to the inverter bridge
thyristors must be slightly longer.

 The

delay for the switching for the control circuit

is 0.1% that of the minimum gate pulse time to
the inverter bridge and will be of no consequence
to the overall operation of the inverter circuit.

Control Circuit :
The

only actual connection of the gate control

circuit to the main thyristor firing circuit of the
UPS is the MOSFET transistor, which is placed in
series with the gate leads of the thyristors.
The MOSFET has nearly infinite input impedance
so any unwanted signals from the gate control
circuit are isolated from the main firing circuit
boards and will not affect the overall operation of
the inverter.

7. Conclusions :
The

modifications to the UPS firing circuits

will significantly reduce the chances of an
inverter trip due to system transients.

The

additional components will have a

negligible impact on the thyristor firing
circuits while preventing unwanted gate
signals to the thyristors for all but 18ns of
each firing cycle.

The

circuit is inexpensive to implement and

is cost effective when compared to possible
down time.

8. References :
[1] Static UPS Failures-Origin and Possible
Prevention H. Wysocki, K. Yackel, Niagara Mohawk
Power Corp.
[2] Niagara Mohawk Deficiency Report 1-96-2575,
UPS F2 Fuse Actuations,2/20/ 1996.
[3] Correspondence with the manufacturer of the
UPS units, Solid-State Controls Inc.
[4] Muhammad Harunur Rashid, Power
Electronics: Circuits, Devices, and Applications,
Prentice Hall, Englewood Cliffs, NJ. 1988.

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