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P- Diffusion
PMOS Enhancement Transistor
n- Diffusion
Poly silicon
Metal 1
Contact cut
N implant
Demarcation line
Substrate contact
Buried Contact
D
A
GND
GND
PMOS
NMOS
GND
Fig 2 Drawing Pmos and Nmos Transistors between Supply rails
PMOS
A
S
NMOS
GND
Fig 3 Combining Gate of Pmos and Nmos Transistors and giving common input
With same gate poly silicon metal
PMOS
A
S
NMOS
GND
Fig 4 Combining Drain pf Pmos and Nmos Transistors to take output with metal 1
PMOS
D
B
A
S
NMOS
GND
Fig 5 Take the output with the poly silicon metal
PMOS
B
A
S
NMOS
GND
Fig 6 Connect the source of Pmos to VDD and Nmos to GND
VDD
PMOS
B
A
S
NMOS
GND
Fig 7 Connect the contact cuts where the different metals are connected
VDD
PMOS
B
A
S
NMOS
Substrate contact
Fig 8 Final CMOS Inverter
GND
GND
FIG 9 Supply rails
GND
Fig 10 Drawing P and N Diffusion between Supply rails
D
A
D
B
GND
Fig 11 Drawing the poly silicon for two different inputs and
identify the source and drain
D
A
D
B
GND
Fig 12 Connect the source of Pmos to VDD and Nmos to GND and
subtrate contacts of both
D
A
D
B
GND
D
A
D
B
GND
Fig 14 Connect the contact cuts where the different metals are connected
LAYOUT
P diffusion
N diffusion
2
P diffusion
N diffusion
1
P diffusion
2
P diffusion
METAL 1
3
METAL 1
4 1
NMOS
ENHANCEMENT
2
NMOS
DEPLETION
PMOS
ENHANCEMENT
2
2
2
2
6 x
6
CMOS INVERTER
LAYOUT
VDD
VSS
VDD
ND
PD
VSS
VDD
ND
D
P
O
L
Y
D
S
PD
VSS
VDD
ND
S
P
O
L
Y
S
PD
VSS
VDD
SUB
CONT
ND
INPU
T
P
O
L
Y
OUTPU
T
PD
VSS
SUB
CONT
CMOS NAND
LAYOUT
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
SUB
CONT
D
VSS
SUB
CONT
VDD
SUB
CONT
D
OUTPU
T
VSS
SUB
CONT
Scaling
VLSI technology is constantly evolving towards
smaller line widths
Reduced feature size generally leads to
better / faster performance
More gate / chip
More accurate description of modern technology is
ULSI (ultra large scale integration)
Characteristics Of
Technology:
Minimum feature size
No. of gates on one chip
Power dissipation
Maximum operation frequency
Die Size
Production cost
Scaling Factors
In our discussions we will consider 2 scaling
factors, and
1/ is the scaling factor for VDD and oxide
thickness tox
1/ is scaling factor for all other linear
dimensions.
Transistor Current
Transistor Delay
Switching Energy
Power Dissipation Per
Gate (Static and
Dynamic)
Power Dissipation Per
Unit Area
Power - Speed Product
MOSFET Scaling
SCALING - refers to ordered reduction in dimensions of
the MOSFET and other VLSI features
Methods of Scaling:
1) Constant Field Scaling
2) Constant Voltage Scaling
3) Lateral Scaling
3. Lateral Scaling
Only the gate length is scaled L = 1/a (gate-shrink).
Year
1980
1983
1985
1987
1989
1991
1993
1995
Feature Size(mm)
5.0
3.5
2.5
1.75
1.25
1.0
0.8
0.6
Area is reduced by 2,
it is advantage.
Cox is scaled by
After Scaling :
Cg is scaled by
/2
Cx is scaled by
1/
After Scaling :
QON is scaled by
1
RON is scaled by
1
Td is scaled by /
2
After Scaling :
As Td Scaled by / 2
fo is scaled by 2 /
Ids is scaled by 1/
J is scaled by 2/
Eg is scaled by
1/2
Pg is scaled by 1/2
Pa is scaled
by 2/2
PT is scaled by
1/2
PARAMETER
SCALING MODEL
Constant Constant Lateral
Field
Voltage
Length (L)
1/ 1/ 1/
Width (W)
1/ 1/
1
Supply Voltage (V)
1/ 1
1
Gate Oxide thickness (tox)
1/ 1/
1
Junction depth (Xj)
1/ 1/ 1
Current (I)
1/
Electric Field
1
1
Load Capacitance (C)
1/1/
1/
Gate Delay (T)
1/1/ 1/
Scaling of Interconnects
Resistance of track R ~ L / wt
R (scaled) ~ (L / ) / ( (w/ )* (t
/))
R(scaled) = R
therefore resistance increases with
scaling