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State Assignment
Device with two states capable of storing information: delay element with
output y
input Y and
x2
FSM: Definitions
FSMs: whose past histories can affect their future behavior in only a finite
number of ways
Serial adder: its response to the signals at time t is only a function of
these signals and the value of the carry at t-1
Thus, its input histories can be grouped into just two classes: those
resulting in a 1 carry and those resulting in a 0 carry at t
Thus, every finite-state machine contains a finite number of memory
devices: which store the information regarding the past input history
devices
sequence to it
Final state: state of the machine after the application of the input
sequence
Most widely used memory elements: flip-flops, which are made of latches
Latch: remains in one state indefinitely until an input signals directs it to do otherwise
Set-reset of SR latch:
SR Latch (Contd.)
Excitation characteristics and requirements:
Trigger or T Latch
Value 1 applied to its input triggers the latch to change state
Excitations requirements:
The JK Latch
Unlike the SR latch, J = K = 1 is permitted: when it occurs, the latch acts
the complement state
Excitation requirements:
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The D Latch
The next state of the D latch is equal to its present excitation:
y(t+1) = D(t)
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Clock Timing
Clocked latch: changes state only in synchronization with the clock pulse
and no more than once during each occurrence of the clock pulse
Duration of clock pulse: determined by circuit delays and signal
propagation time through the latches
Must be long enough to allow latch to change state, and
Short enough so that the latch will not change state twice due to the same
excitation
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Master-slave Flip-flop
Master-slave flip-flop: a type of synchronous memory element that
eliminates the timing problems by isolating its inputs from its outputs
Master-slave SR flip-flop:
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D flip-flop
Master-slave D flip-flop avoids the above problem: even when a static
hazard occurs at the D input when the clock is high, the output of
the master latch reverts to its old value when the glitch goes away
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Edge-triggered Flip-flop
Positive (negative) edge-triggered D flip-flip: stores the value at the D input
transition
Any change at the D input after the clock has made a transition does not have any effect on the value stored in the flip-flop
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Sequence Detector
One-input/one-output sequence detector: produces output value 1 every
sequence 0101 is detected, else 0
time
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z = xy1y2
y1 = xy1y2 + xy1y2 + xy1y2
y2 = y1y2 + xy1 + y1y2
Logic diagram:
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Binary Counter
One-input/one-output modulo-8 binary counter: produces output value 1 for
every eighth input 1 value
State diagram and state table:
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T1 = x
T2 = xy1
T3 = xy1y2
z = xy1y2y3
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S1 = xy1
R1 = xy1
S2 = xy1y2
R2 = xy1y2
S3 = xy1y2y3
R3 = z = xy1y2y3
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Parity-bit Generator
Serial parity-bit generator: receives coded messages and adds a parity bit
to every m-bit message
Assume m = 3 and even parity
J1 = y2
K1 = y2
J2 = y1
K2 = y 1
J3 = xy1 + xy2
K3 = x + y2 25
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Example (Contd.)
Sequential circuit M:
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Example (Contd.)
Sequential circuit M:
K, u, z: initially at 0
When u = 1: computation starts by setting = 1
Causes b to be loaded into X
To add a to x: set = 1 and = 1 to keep track of the number of times a has
been added to x
After four such additions: z = 1 and the computation is complete
At this point: K = 0 to be ready for the next computation
State diagram:
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Example (Contd.)
State assignment, transition table, maps and logic diagram:
= y1y2
==yy
1 2
z = y1y2
Y1 = y 2
Y2 = y1y2 + uy1 + Ly2
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A Computing Machine
FSMs: called non-writing since they cannot write or change their input
symbols
Tape divided into squares: each square stores a single symbol at any moment blank squares store 0
Head can perform three operations: reading, writing, and shifting
FSM: control unit specifies the operations to be executed by the head
Cycle of computation: machine starts in some state Si, reads the symbol currently being scanned by the head,
writes a new symbol there, shifts right or left, and then enters state Sj
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Computation Example
Example: initial pattern on the tape two finite blocks of 1s separated by a
finite block of blanks
Shift the left-hand block of 1s to the right: until it touches the right-hand
block, and then halt
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be
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Iterative Networks
Iterative network: cascade of identical cells
Sequential: counter, shift register
Combinational
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Cell Table
Cell table: analogous to state table
Example: 0101 pattern detector
Assuming the same assignment for states (A: 00, B: 01, C: 11, D: 10):
each cell same as the combinational logic of the sequential circuit derived
for the 0101 sequence detector earlier
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Synthesis
Example: synthesize an n-cell iterative network
Each cell has one cell input xi and one cell output zi
zi = 1: if and only if either one or two of the cell inputs x1, x2, , xi have
value 1
States A, B, C, D: 0, 1, 2, (3 or more) of the cell inputs to preceding cells
have value 1
Cell table
Cell
Output-carries and cell-output table
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