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Chapter 2
Circuit Switch Design
Principles
..
.
Outputs
1
2
..
.
Strictly Nonblocking
Bar State
Cross State
Strictly Nonblocking
1
Connections:
2
Inputs
3
Input 1 to Output 3
Input 2 to Output 4
4
1
2
3
Outputs
Blocking
1
2
1
2
3
4
3
4
Nonblocking Properties
RNB
WSNB
SNB
Rearrangeably Nonblocking
1
Rearrangements
1
2
3
4
1
2
3
4
Connection cannot
be set up between
input 4 and output
1
1
2
3
4
1
2
3
4
Connection can
now be set up
between input 4
and output 1
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
Input 1234
Output 1234
..
.
..
.
..
.
..
.
(a)
Bandwidth
expansion factor
(b)
=m
10
1
2
3
4
1
2
3
4
11
1
2
.
.
.
.
.
.
1
2
N! mappings
M crosspoints
#states #mappings
2M N!
M log2 N!
Nlog2 N
forlarge N
12
...
...
...
n1 r 2
r1 r3
r 2 n3
(1)
(1)
(1)
n1 r 2
r1 r3
r 2 n3
(2)
(2)
(2)
n1 r 2
r1 r3
r 2 n3
(r1)
(r2)
(r3)
..
.
..
.
...
...
...
ri # switch
modules
in
column i
n1 # inputs
in
column 1
module
n3 # outputs
in
column 3
module
r2 n1 ,n3
Necessary
condition for
Fig. 2.6. A three-stage clos switch
architecture
nonblocking:
13
1
2
3
4
5
6
7
8
9
F
G
A
1
2
3
4
5
6
7
8
9
Key:
Find a
commonly
accessible
middle node
from both
input and
output nodes
F
G
A
H
1
Stage 3
switch
r2
1
2
Stag
e1
switc
h
F,G,H
r1
Fig. 2.8. The connection matrix of the three-stage
network
15
Fundamental Conditions
Conditions of a Legitimate connection Matrix :
1. SA n1 ,
2. SB n3 ,
3.
r2 n1
r2 n3
16
r2 min n1 n3 1,N
Proof: Trivial case: N n1 n3 1
If n1 n3 1 N:
Worst case: all other inputs of A and outputs of B are busy
SA n1 1
SB n3 1
SA U SB SA SB SA I SB
SA SB
n1 n3 2
if r2 n1 n3 1 ,
there is at least one available middle-stage node
17
Rearrangement
Substituting symbols in connection matrix
such that
1.) Matrix remains legitimate
2.) An unused symbol in row A and column B can
be found
18
SA
SB
B
Chain
terminates at A
A because
A
D
A C
C SA
A
C
B B
D C
SA SB r2
Connection
between A and B is
blocked
C SB
D SA
..
A
..
..
..
A already
B already
B
C
..
connecte
connecte
A
..
..
d to all
d to all
B
..
A
middlemiddleD
..
B
stage
stage
.
.
A
..
nodes
nodes
..
except
D links used by connections in the
except
Only
chain C
are shown
Fig. 2.9. (b) Physical connections corresponding to the chain
20
There should be
two end points in
a chain
B
A
B B
D can now be
put in entry (A,
B)
C D
A
C
A C
D
A
..
A
..
..
A
..
..
..
C
..
..
..
B
..
B
..
..
...D
...D
C
D
A
Fig. 2.12. (a) Two chains, one originates from B, one from A
This
column
search
ends in C,
which is
not
possible
...
Start searching
from B. Column
search always
looks for D
2x2
3
4
2x2
...
N-1
N
2x2
..
..
N N
2 2
N N
2 2
..
..
2x2
1
2
2x2
3
4
2x2
N-1
N
...
1
2
3
4
3
4
5
6
5
6
7
8
7
8
Baseli
ne
Netwo
rk
Rever
se
Baseli
ne
Fig. 2.14. An 8x8 Benes
Netwo
Network rk
27
Reverse Baseline
Network
28
Looping Algorithm
1
2
1
2
3
4
3
4
5
6
5
6
7
8
7
8
29
30
Cantor Network
1
2
.
.
.
..
..
..
..
..
m=1
..
..
.
.
.
m = log N
Fig. 2.16. Cantor network
31
Ai 2 - 1
i
Check:
log2 N
A N1
i 1
An example of 8 x8 Benes
network
32
#middle nodes
eliminated
log2 N1
i 1
N
AB
(log2 N 1)
i i
4
Nm
N
2 (log2 N -1)
2
4
m log2 N -1
33
1
2
3
4
3
4
5
6
5
6
7
8
7
8
If input 4 is connected to
Therefore the two lower
this link: a subtree is
middle-stage nodes are
formed by the three
eliminated from
subsequent nodes
connection by input 3
Fig. 2.17. Binary tree extended from an input
to
all middle-stage nodes
34
1
2
4
..
.
..
.
N
N
N
N
2 ... 1 0
4
8
4
2
35
Time-Domain Switching
D
E
M
U
X
D
E
M
U
X
36
Time-Domain Switching
TSI
Write
Write
Address
Sequence =
a, b, c
Read
a
b
c
RAM
Read
Address
Sequence =
b, a, c
37
Time-Space-Time Switching
n
TSI
TSI
TSI
TSI
..
.
rxr
TSI
..
.
TSI
39
Time-Space-Time Switching
( i, j ) data on input i at time-slot j
Frame
C(1,3)B(1,2)A(1,1)
1
3
2
TSI
F(2,3)E(2,2)D(2,1)
3
1
1
TSI
L(3,3)H(3,2)G(3,1)
2
2
3
TSI
TSI
3x3
TSI
TSI
Targeted Outputs
Fig. 2.25 A time-space time
switch
40
Time-Space-Time Switching
A(1,1)
B(1,2)
C(1,3)
M CBA
U
X
D(2,1)
E(2,2)
F(2,3)
M
FED
U
X
G(3,1)
H(3,2)
L(3,3)
M
LHG
U
X
TSI
TSI
TSI
BAC
EDC
(1)
EDF
HAL
(2)
HGL
(3)
BGF
TSI
M
CED
U
(1) X
D(2,1)
E(2,2)
C(1,3)
TSI
M
LHA
U
(2) X
A(1,1)
H(3,2)
L(3,3)
TSI
M
GBF
U
(3) X
G(3,1)
B(1,2)
F(2,3)
B(1,2)A(1,1)C(1,3)
E(2,2)D(2,1)F(2,3)
E(2,2)D(2,1)C(1,3)
3x3
H(3,2)G(3,1)L(3,3)
H(3,2)A(1,1)L(3,3)
B(1,2)G(3,1)F(2,3)
Time Slot 1
Time Slot 2
Time Slot 3
A(1,1)
B(1,2)
C(1,3)
D(2,1)
E(2,2)
F(2,3)
G(3,1)
H(3,2)
L(3,3)
(1)
(2)
(3)
(2)
(3)
(3)
G(3,1)
B(1,2)
F(2,3)
Module (i)
Module (i)
Module (i)
corresponds
corresponds
corresponds
to time slot i of
to output TSI (i) in
to input TSI (i) in
space-division
time-space-time
time-space-time
switch in
switch switching
switch
Fig. 2.22. Equivalent
of
time-space-time
time-space-time
switch and
43