IEG4020

Telecommunication Switching and Network Systems

Chapter 2
Circuit Switch Design
Principles

Space-Domain Circuit Switching

Inputs
1
2

..
.

Outputs
1
2

..
.

Fig. 2.1. An N x N switch used to interconnect N

inputs
and N outputs

Strictly Nonblocking

Bar State

Cross State

Fig. 2.2. Bar and cross states of 2 x 2 switching

elements

Strictly Nonblocking
1

Connections:

2
Inputs
3

Input 1 to Output 3
Input 2 to Output 4

4
1

2
3
Outputs

Fig. 2.3. (a) Crossbar

switch
4

Blocking
1
2

1
2

3
4

3
4

Blocking: Input 2 cannot be connected to

output 2
if input 1 is already connected
to output 1
Fig. 2.3. (b) banyan
switch

Nonblocking Properties
RNB
WSNB
SNB

RNB Rearrangeably Nonblocking

WSNB
Wide-sense Nonblocking
SNB Strictly Nonblocking
6

Rearrangeably Nonblocking
1

Fig. 2.4. (a) A 4 x 4 rearrangeably nonblocking

switch

Rearrangements
1
2
3
4

1
2
3
4

Connection cannot
be set up between
input 4 and output
1

Fig. 2.4. (b) a connection request from input 4 to output 1 is blocked

1
2
3
4

1
2
3
4

Connection can
now be set up
between input 4
and output 1

Fig. 2.4. (c) Same connection request can be satisfied by rearranging

the existing connection from input 2 to output 2

Two states corresponding to the same mapping :

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

Input 1234
Output 1234

Complexity of nonblocking switches :

How to build large switch from smaller switches?

Problems with two-stage networks :

n
1
1
1
1
n N = mn
# lines
=
m2 n
2
2
2
2
= mN

..
.

..
.

..
.

..
.

(a)

Bandwidth
expansion factor

(b)

=m

10

1
2
3
4

1
2
3
4

Fig. 2.5. (a) An example of one-to-one mapping from

input to output

11

1
2

.
.
.

.
.
.

1
2

N! mappings
M crosspoints
#states #mappings
2M N!
M log2 N!

Nlog2 N
forlarge N

Fig. 2.5. (b) Number of crosspoints needed for

nonblocking switch

12

Clos Switching Network

...
...
...

n1 r 2

r1 r3

r 2 n3

(1)

(1)

(1)

n1 r 2

r1 r3

r 2 n3

(2)

(2)

(2)

n1 r 2

r1 r3

r 2 n3

(r1)

(r2)

(r3)

..
.

..
.

n1r1 = n3r3 = N for N N switch

...
...
...

ri # switch
modules
in
column i
n1 # inputs
in
column 1
module
n3 # outputs
in
column 3
module

r2 n1 ,n3

Necessary
condition for
Fig. 2.6. A three-stage clos switch
architecture
nonblocking:
13

1
2
3
4
5
6
7
8
9

F
G
A

1
2
3
4
5
6
7
8
9

Key:
Find a
commonly
accessible
middle node
from both
input and
output nodes

A request for connection from input 9 to output 4 is bl

SA = middle-stage nodes used by A
= { F, G }
SB = middle-stage nodes used by B
={H}
Fig. 2.7. An example of blocking in a three-stage
switch
14

F
G
A

H
1

Stage 3
switch

r2

1
2
Stag
e1
switc
h

F,G,H

r1
Fig. 2.8. The connection matrix of the three-stage
network

15

Fundamental Conditions
Conditions of a Legitimate connection Matrix :

1. SA n1 ,

SA number of symbols in row A

2. SB n3 ,

SB number of symbols in row B

3.

r2 n1
r2 n3

necessary condition for

nonblocking property

4. Symbols in each row (column) must be distinct

SA , SB r2

16

Condition for Strictly Nonblocking

Clos network is strictly nonblocking if

r2 min n1 n3 1,N
Proof: Trivial case: N n1 n3 1
If n1 n3 1 N:
Worst case: all other inputs of A and outputs of B are busy
SA n1 1
SB n3 1
SA U SB SA SB SA I SB
SA SB
n1 n3 2
if r2 n1 n3 1 ,
there is at least one available middle-stage node
17

Condition for Rearrangeably

Nonblocking
Rearrangeability allows condition to be reduced to
r2 max n1 , n3

Rearrangement
Substituting symbols in connection matrix
such that
1.) Matrix remains legitimate
2.) An unused symbol in row A and column B can
be found

18

Condition for Rearrangeably

Nonblocking
Proof: i)"Only if " part trivial
ii) "if " part
SA n1 1
S n 1
3
B

SA

SB

a.) SA U SB r2 an unused symbol

b.) SA U SB r2
SA SB SA U SB SB
r2 (n3 1) 1
SB SA r2 (n1 1) 1
a symbol C in row A, not in column B
a symbol D not in row A, but in column B
19

B
Chain
terminates at A
A because
A
D
A C
C SA
A
C

B B
D C

SA SB r2
Connection
between A and B is
blocked
C SB

D SA

Fig. 2.9. (a) A chain of C and D originating from B

..
A
..

..

..

A already
B already
B
C
..
connecte
connecte
A
..
..
d to all
d to all
B
..
A
middlemiddleD
..
B
stage
stage
.
.
A
..
nodes
nodes
..
except
D links used by connections in the
except
Only
chain C
are shown
Fig. 2.9. (b) Physical connections corresponding to the chain
20

D occurs twice in this

column, making the
matrix illegitimate (i.e.
physically impossible
in associated switch)

A loop in the chain

There should be
two end points in
a chain

Fig. 2.10. Illustration showing loops in chains are not

permitted in legitimate connection matrix
21

B
A

B B

D can now be
put in entry (A,
B)

C D

A
C
A C
D
A

Fig. 2.11. (a) Rearrangement of the chain in Fig. 2.9.

..
A
..

..
A
..

..

..
C

..

..

..
B

..
B
..

..

Fig. 2.11. (b) Corresponding rearrangement of connections

22

...D
...D
C

D
A

Fig. 2.12. (a) Two chains, one originates from B, one from A

This
column
search
ends in C,
which is
not
possible

...

Start searching
from B. Column
search always
looks for D

Fig. 2.12. (b) Illustration that the two chains cannot be

connected
23

How many rearrangements?

o A new row/column is covered each time a
point is included
o (r1 + r3 2) other rows and columns
o At most (r1 + r3 1) rearrangements (loose)

Can do better: #rearrangements min(r1 ,r3) 1

o Basic: consider two chains, one originates from row A,
one from column B
Choose the shorter chain for rearrangement
o A composite move: a move in chain 1 with a move in
chain 2
At most r1 2 moves before all rows exhausted
At most r3 2 moves before all columns exhausted
24

Benes Switching Network

1
2

2x2

3
4

2x2

...

N-1
N

2x2

..
..

N N

2 2

N N

2 2

..
..

2x2

1
2

2x2

3
4

2x2

N-1
N

...

The N x N network is rearrangeably nonblocking if

N N
the networks are rearrangeably nonblocking
2 2
Fig. 2.13. Recursive decomposition of a
rearrangeably nonblocking network
25

Benes Network - Complexity

Number of 2x2 elements in Benes Network :

Let N 2n and f(k) #stages in k x k Benes Network, then

N
f (N) f ( ) 2
2
f(2n) (2n-1) 2
f (2n-2) 4
.
.
f (2n- j ) 2j
f (2) 2(n-1)
1 2(n-1)
2n-1 2log2 N 1
26

Benes Network - Structure

1
2

1
2

3
4

3
4

5
6

5
6

7
8

7
8

Baseli
ne
Netwo
rk

Rever
se
Baseli
ne
Fig. 2.14. An 8x8 Benes
Netwo
Network rk
27

Baseline and Reverse Baseline

Networks
Baseline
Network

Reverse Baseline
Network

28

Looping Algorithm
1
2

1
2

3
4

3
4

5
6

5
6

7
8

7
8

Set up paths for input-output

pairs :
input 12345678
(1, 4), (2, 5), (3, 6), (4, 3)
output 45637812
(5, 7), (6, 8), (7, 1), (8, 2)
Central Algorithm: # steps =
Fig.
2.15. Illustration of a looping connection setup algorithm
N logN

29

Properties of Benes Network

1.)
Unique path property of underlying baseline
and reverse baseline networks
2.) Binary tree to middle-stage nodes
An input can reach 2j-1 nodes at stage j, j <= log2N
3.) Reachability of nodes in baseline/reverse baseline
networks:
A node in stage i can be reached by 2 i inputs and
can reach 2n-j+1 outputs
4.) Middles nodes blocked by an existing path

30

Cantor Network
1
2

.
.
.

..
..

..
..
..

m=1

..

..

.
.
.

m = log N
Fig. 2.16. Cantor network
31

Cantor Network Strictly

Nonblocking

Cantor Network is SNB :

1.) Let m be # of Benes Network required
2.) Worst case: all other N-1 inputs/outputs busy
there are (N-1) paths to middle nodes
3.) One path meets the binary tree at stage 1
Two paths at stage 2
Let the #paths meeting the binary trees at stage i be Ai
Stage 1Stage 2

Ai 2 - 1
i

Check:

log2 N

A N1
i 1

An example of 8 x8 Benes
network
32

Cantor Network Strictly

Nonblocking
4.) A node in stage i blocks
Bi 2ni 1 middle nodes
(e.g. i 1, half the nodes or 2n-2 nodes are blocked)

#middle nodes
eliminated

log2 N1

i 1

N
AB
(log2 N 1)
i i
4

#middle nodes eliminated

by inputs and outputs

5.) #middle nodes >

Nm
N
2 (log2 N -1)
2
4
m log2 N -1
33

Connection paths from inputs 1 and

2 intersect with binary tree from
the first time in stage 2
1
2

1
2

3
4

3
4

5
6

5
6

7
8

7
8

If input 4 is connected to
Therefore the two lower
this link: a subtree is
middle-stage nodes are
formed by the three
eliminated from
subsequent nodes
connection by input 3
Fig. 2.17. Binary tree extended from an input
to
all middle-stage nodes
34

# middle nodes blocked from

inputs
Number of paths

Number of middle-stage nodes blocked

N
4
N
8
N
16

1
2
4

..
.

Total number of middle

..
.

N
N
N
N
2 ... 1 0
4
8
4
2

nodes blocked from inputs

N
(log2 N 1)
4

35

Time-Domain Switching

D
E
M
U
X

D
E
M
U
X

Space division switch

Fig. 2.18. Performing time-slot interchange using

space-division switch

36

Time-Domain Switching
TSI

Write

Write
Address
Sequence =
a, b, c

Read

a
b
c
RAM

Read
Address
Sequence =
b, a, c

Switching in time domain

Fig. 2.19. Direct time slot interchange using random
access memory (switching in the time domain)

37

Example for Time-Domain

Switching
Example: memory access time
T 1 rate 1.5Mbps
N 24
Each data source is 64 kbps
One byte per time-slot
24 x 64,000 bps
Arrival rate =
8 bits/time-slot
=192,000 time-slots/sec
A read and a write required per time-slot
1
memory access time
2.6 s
2 x 192,000
38

Time-Space-Time Switching
n

TSI

TSI

TSI

TSI

..
.

rxr

TSI

..
.

TSI

n, m : number of time slots per frame at various poin

Fig. 2.20. A time-space-time
switch

39

Time-Space-Time Switching
( i, j ) data on input i at time-slot j
Frame
C(1,3)B(1,2)A(1,1)
1
3
2

TSI

F(2,3)E(2,2)D(2,1)
3
1
1

TSI

L(3,3)H(3,2)G(3,1)
2
2
3

TSI

TSI
3x3

TSI
TSI

Targeted Outputs
Fig. 2.25 A time-space time
switch
40

Time-Space-Time Switching
A(1,1)
B(1,2)
C(1,3)

M CBA
U
X

D(2,1)
E(2,2)
F(2,3)

M
FED
U
X

G(3,1)
H(3,2)
L(3,3)

M
LHG
U
X

TSI

TSI

TSI

BAC

EDC

(1)

EDF

HAL

(2)

HGL

(3)

BGF

TSI

M
CED
U
(1) X

D(2,1)
E(2,2)
C(1,3)

TSI

M
LHA
U
(2) X

A(1,1)
H(3,2)
L(3,3)

TSI

M
GBF
U
(3) X

G(3,1)
B(1,2)
F(2,3)

Fig. 2.21. Equivalent of time-space-time switching

and
three-stage space switching
41

B(1,2)A(1,1)C(1,3)
E(2,2)D(2,1)F(2,3)

E(2,2)D(2,1)C(1,3)

3x3

H(3,2)G(3,1)L(3,3)

H(3,2)A(1,1)L(3,3)
B(1,2)G(3,1)F(2,3)

( i, j ) data on input i at time slot j

Time Slot 1

Time Slot 2

Time Slot 3

Fig. 2.21. Input-output mapping changes from

slot to slot in
space-division switch in time-space-time
switching
42

A(1,1)
B(1,2)
C(1,3)
D(2,1)
E(2,2)
F(2,3)
G(3,1)
H(3,2)
L(3,3)

(1)

(2)

(3)

These lines correspond to time slot 1

D(2,1)
E(2,2)
C(1,3)
(1)
(1)
A(1,1)
H(3,2)
L(3,3)
(2)

(2)

(3)

(3)

G(3,1)
B(1,2)
F(2,3)

Module (i)
Module (i)
Module (i)
corresponds
corresponds
corresponds
to time slot i of
to output TSI (i) in
to input TSI (i) in
space-division
time-space-time
time-space-time
switch in
switch switching
switch
Fig. 2.22. Equivalent
of
time-space-time
time-space-time
switch and

three-stage space switching

~END~

43