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Chapter 9
9.1 Introduction
Digital Circuits
Fig. 9.1
Block diagram
of an
asynchronous
sequential
3
Digital Circuits
no clock pulse
difficult to design
delay elements: the propagation delay
must attain a stable state before the input is
changed to a new value
Digital Circuits
The procedure
Digital Circuits
Examples
Fig. 9.2
Example of an
asynchronous
sequential
circuit
Y1 = xy1+ x'y2
Y2 = xy1' + x'y2
Digital Circuits
Fig. 9.3
Maps and
transition
table for the
circuit of
Fig. 9.2
Y=y
Digital Circuits
The difference
Digital Circuits
Digital Circuits
A flow table
Fig. 9.4
Example of
flow tables
Fig. 9.5
Derivation of a
circuit specified
by the flow
table of Fig.
9.4(b)
Digital Circuits
11
Race conditions
00 10 11 or 00 01 11
a noncritical race
Digital Circuits
12
Noncritical race
Fig. 9.6
Examples of
non-critical
Digital Circuits
13
Critical race
Fig. 9.7
Examples of critical
races
Digital Circuits
14
A cycle
Digital Circuits
15
A cycle
Fig. 9.8
Examples of cycles
Digital Circuits
16
Stability Considerations
Fig. 9.9
Example of an
unstable circuit
Digital Circuits
17
Digital Circuits
18
Fig. 9.10
SR latch with NOR gates
Digital Circuits
19
S'R' = 0
Y = (S(Ry)')' = S'+ Ry when S'R' = 0
S'R' latch
Digital Circuits
20
Fig. 9.11
SR latch with NAND gates
Digital Circuits
21
Analysis example
Fig. 9.12
Examples
of a circuit
with SR
latch
Digital Circuits
22
S1 = x1y2
R1 = x'1x'2
S2 = x1x2
R2 = x'2y1
S1R1 = x1y2x'1x'2 = 0
S2R2 = x1x2x'2y1 = 0
Digital Circuits
23
instead of 0000
Fig. 9.13
Transition table for the circuit of Fig.
9.12
Digital Circuits
24
Analysis procedure:
Digital Circuits
25
Digital Circuits
26
Implementation Example
Digital Circuits
27
Fig. 9.14
Derivation of
a latch
circuit from a
transition
table
Digital Circuits
28
Latches
derive a pair of maps for Si and Ri
Digital Circuits
29
Debounce circuit
Fig. 9.15
Debounce circuit
30
Design specifications
a gated latch
two inputs, G (gate) and D (data)
one output, Q
G = 1: Q follows D
G = 0 : Q remains unchanged
Digital Circuits
31
Fig. 9.16
Primitive flow table
Digital Circuits
34
Fig. 9.17
Reduction of the primitive flow table
Digital Circuits
35
State assignment
a:0, b:1
Fig. 9.18
Transition table and output map for gated latch
Digital Circuits
36
the output
logic diagram
Fig. 9.19
Gated-latch logic diagram
Digital Circuits
37
SR latch implementation
Fig. 9.20
Circuit with SR latch
Digital Circuits
38
Fig. 9.21
Assigning output
values to unstable
states
Digital Circuits
39
Digital Circuits
40
Summary
Digital Circuits
41
Equivalent states
Digital Circuits
42
Digital Circuits
43
Implication Table
Digital Circuits
44
Fig. 9.22
Implication table
Digital Circuits
45
Digital Circuits
46
47
Compatible pairs
Fig. 9.23
Flow and
implication
tables
Digital Circuits
48
Maximal compatibles
Fig. 9.24
Merger diagram
Digital Circuits
49
Fig. 9.24
Merger diagram
Digital Circuits
50
(a,c,d) (b,e,f)
another example
Digital Circuits
51
Fig. 9.25
Choosing a set
of compatibles
Digital Circuits
52
(a,b) (c,d,e)
Digital Circuits
53
Fig. 9.26
Three-row flow-table example
Digital Circuits
54
Fig. 9.27
Flow-table with an extra row
Digital Circuits
55
Transition Table
Fig. 9.28
Flow-table with an extra row
Digital Circuits
56
Fig. 9.29
Four-row flow-table example
Digital Circuits
57
Fig. 9.30
Choosing extra rows for the flow table
Digital Circuits
58
Fig. 9.31
State assignment
to modified flow
table
Digital Circuits
59
Multiple-row method
less efficient
multiple equivalent
states for each state
Fig. 9.32
Multiple-row assignment
Digital Circuits
60
9-7 Hazards
Digital Circuits
61
examples
Fig. 9.33
Circuits with hazards
Digital Circuits
62
Fig. 9.34
Types of hazards
Digital Circuits
63
Y = (x1+x2')(x2+x3)
The remedy
Fig. 9.35
Maps illustrating a hazard and its removal
Digital Circuits
64
Hazard-free circuit
Fig. 9.36
Hazard-free circuit
Digital Circuits
65
Fig. 9.37
Hazard in a
asynchronous
sequential
circuit
Digital Circuits
66
111 110
111 010
Digital Circuits
67
Fig. 9.38
Latch implementation
Digital Circuits
68
Digital Circuits
69
Essential Hazards
Digital Circuits
70
Digital Circuits
71
Design Specification
Digital Circuits
72
Fig. 9.39
Primitive flow table
Digital Circuits
73
Fig. 9.40
Implication table
Digital Circuits 74
Fig. 9.41
Merger diagram
Digital Circuits
75
Fig. 9.42
Reduced flow table
Digital Circuits
76
Fig. 9.43
Transition diagram
Digital Circuits
77
Fig. 9.44
Transition table and output map
Digital Circuits
78
Logic Diagram
Fig. 9.45
Maps for latch
inputs
Digital Circuits
79
Logic Diagram
Fig. 9.46
Logic diagram of negativeedge-triggered T flip-flop
Digital Circuits
80