MEMORY ELEMENTS

Flip-flops and Latches

Interpret the following code:

signal Y,D,En : std_logic;
...........

Y <= D when En=1;

--else is missing
-- the same with process
process (En,D)
begin
if (En=1) then
Y <= D;
--else is missing
end if;
end process;

U22
D0
D1
S0
MUX2

En

How a missing else is interpreted in hardware ?

Exactly as in software! The object should preserve its
value!
OK! But how?
2

This is a latch!
It is able to store a bit!
A latch is a memory
element.

U22
D0
D1
S0
MUX2

En

In fact a latch is never implemented like this!

Recall!
D
Y
S_bar

Y_bar
Q_bar
R_bar

An R-S latch!

En

When Q output will change its value?

The simulator executes the
process when En, En, D or D

--Latch
process (En,D)
begin
if (En=1) then
Q <= D;
end if;
end process;

Q
1.
2.
3.

<= D when:
En (0 1) regardless D
D and En=1
D and En=1

En has no effect

The simulator executes the process when there is an

event on En or D.
Event means a transition 01 or a transition 10.
The 01 transition is called rising edge:
The 10 transition is called falling edge:
4

When the Q output will change its value?

--Latch
process (En,D) -En,
begin
if (En=1) then
Q <= D;
end if;
end process;

G
ILD

A small change: remove D from the process

sensitivity list
process (En) -En
Q <= D
begin
only when En (0 1)
if (En=1) then
regardless D
Q <= D;
end if;
end process;
En has no effect
--no longer equivalent to:
Y <= D when En=1;

Q
6

So, what is this?

process (En) -En
begin
if (En=1) then
Q <= D;
end if;
end process;

FD

Its a flip-flop!
Usually the control signal of a FF is named
CLOCK and is abbreviated CLK:
process (Clk)
begin
if (Clk =1) then
Q <= D;
end if;
end process;
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process (Clk)
begin
if (Clk =1) then Q <= D; end if;
end process;

Lets simulate!
First behavioral:

Then post place and route:

Its a Flip-flop!

Its a Latch!

Why the two simulations disagree?

Weve got a synthesis warning:
==============================================================
*
HDL Analysis
*
==============================================================
Analyzing Entity <latch> in library <work> (Architecture <behavioral>).
WARNING:Xst:819 "D:/Users/John/JohnSchool/DisciplinaVHDL/Curs/FR11_FF/Latch/latch.vhd"
line 40:
The following signals are missing in the process sensitivity list: D.

The synthesis adds D to the process sensitivity list.

process (Clk ,D)
)
begin
if (Clk =1) then
Q <= D;
end if;
end process;

The flip-flop
becomes a
latch!
9

Event:
Usually, the synthesis tool ignores the sensitivity list and
builds its own list consisting of all signals appearing
in the right side of an assignment, if conditions and
case selectors.
Consequently, there will be no difference between a Latch
description and a FF description.
We need a method to describe Flip-flops!
Solution:
Well use a member function for signal class called event.
signal a_signal : std_logic;
.....

In synthesis:
returns true if there is an event on
a_signal in the current simulation cycle. 10

a_signalevent

Event (cont):
a_signalevent

returns TRUE for both edges: a_signal

To select the rising edge only:

a_signalevent and a_signal=1
or use the function

rising_edge(a_signal)

To select the falling edge only:

a_signalevent and a_signal=0
or use the function

falling_edge(a_signal)

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Flip-flop description with event:

process (Clk, D) -Clk, D
--process (Clk) -Clk works
begin
if rising_edge(Clk) then
Q <= D;
end if;
end process;
--equivalent to:
Q <= D when rising_edge(Clk);

as well
Q <= D
only when Clk (0 1)
Clk, D, D are rejected

Latch description:

--Latch
process (En,D) -En,
begin
if (En=1) then
Q <= D;
end if;
end process;

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Restriction on edge condition:

1.

In a process, a single edge condition must be tested.

Otherwise we describe something that reacts on
many edges:
signal D1, D2, Clk1, Clk2, Q
........................
process (Clk1, Clk2 )
beginERROR:Xst:827 if"D:/Users/John/JohnSchool/DisciplinaVHDL/Cu
ridsing_edge(Clk1) then
Q <= D1;
rs/FR11_FF/Latch/latch.vhd"
line 40: Signal Q
end if;

cannot be synthesized, bad synchronous

ifdescription.
ridsing_edge(Clk2) then

Q <= D2;
end if;
end process;

No hardware counterpart!
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Restriction on edge condition (cont):

1.

In a process, the edge condition must be the LAST

condition tested in an if elsif elsif instruction.
Otherwise we describe something that reacts on
many edges:
signal D, Clk, Q
........................
process (Clk)
begin
ERROR:Xst:827 if rising_edge(Clk)
then
"D:/Users/John/JohnSchool/DisciplinaVHDL/Cu
Q <= D;
rs/FR11_FF/Latch/latch.vhd" line 40: Signal Q
else
synthesized,
Q cannot
<= 0;be
--falling
edge bad synchronous
description.
end if;
end process;

No hardware counterpart!
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Restriction on edge condition, summary:

1. In a process, test a single edge condition.
2. In a process, the edge condition must be the
LAST condition tested in an if elsif elsif
instruction.
3. Dont mix the edge condition with other tests.
Some synthesis tools wont accept them:
if rising_edge(Clk) and Ce=1

Woks but is not

recommended!

15

Specifying initial value of a Flip-flop

Basic FF description:
signal Clk, D : std_logic;
signal Q
: std_logic;
--...
process(Clk)
begin
if rising_edge(Clk) then
Q <= D;
end if;
end process;

If a Reset button is not necessary:

signal Clk, D : std_logic;
signal Q
: std_logic :=
; 0;
--...
process(Clk)
begin
if rising_edge(Clk) then
Q <= D;
end if;
end process;

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Specifying initial value of a Flip-flop

If Reset button is needed:
signal Clk, D, Rst : std_logic;
signal Q
: std_logic;
--...
Q <= 0 when Rst= 1 else
process(Clk, Rst)
D when rising_edge(Clk);
begin
--equivalent description with
conditional signal assignment.
if Rst= 1 then
--Not recommended!
Q <= 0;
1;
elsif rising_edge(Clk) then
Q <= D;
end if;
end process;

This type of Reset is asynchronous.

The FF will be reset as soon as Rst becomes active,

regardless Clk activity.

The initial value can be 1 instead 0. In this
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case Rst is usually renamed to Set.

Specifying initial value of a Flip-flop

If Reset button is needed:
signal Clk, D, Rst : std_logic;
signal Q
: std_logic;
--...
process(Clk)
Begin
if rising_edge(Clk) then
if Rst= 1 then
Q <= 0;
1;
else
Q <= D;
end if;
end if
end process;

This type of Reset is synchronous.

The FF will be reset on the rising edge of Clk only if Rst is
1
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The initial value can be 1 instead 0.

Specifying initial value of a Flip-flop

If Reset button is needed:
signal Clk, D, Rst : std_logic;
signal Q
: std_logic;
--...
process(Clk)
Begin
if rising_edge(Clk) then
if Rst= 1 then
Q <= 0;
else
Q <= D;
end if;
end if
end process;
Equivalent description with conditional signal
assignment:
Q <= 0 when rising_edge(Clk) and Rst= 1 else
D when rising_edge(Clk) and Rst= 0;
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It is not synthesizable by ISE! Dont use it!

A Flip-flop can have a CE = Clock Enable input

If CE is 0, Clock is ignored!
signal Clk, D, CE: std_logic;
signal Q
: std_logic;
--...
process(Clk)
Begin
if rising_edge(Clk) then
if CE= 1 then
Q <= D;
end if;
end if
end process;

The FF will be written on the rising edge of Clk if and only if

CE is 1

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