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CS 150: concepts/skills/abilities
Basics of logic design (concepts)
Sound design methodologies (concepts)
Modern specification methods (concepts)
Familiarity with full set of CAD tools (skills)
Appreciation for differences and similarities
(abilities) in hardware and software design
New ability: to accomplish the logic design task with the aid of computer-aided
design tools and map a problem description into an implementation with
programmable logic devices after validation via simulation and understanding
of the advantages/disadvantages as compared to a software implementation
Simulation, Chipscope
& Complex System
Description (e.g., SDRAM)
Boolean algebra
Gates
Waveforms
Finite state behavior
Register-transfer behavior
Concurrent abstract specifications
Verilog
Structural
& Behaviorial
Descriptions
Implementation in Software
integercombination_lock(){
integerv1,v2,v3;
integererror=0;
staticintegerc[3]=3,4,2;
while(!new_value());
v1=read_value();
if(v1!=c[1])thenerror=1;
while(!new_value());
v2=read_value();
if(v2!=c[2])thenerror=1;
while(!new_value());
v3=read_value();
if(v2!=c[3])thenerror=1;
if(error==1)thenreturn(0);elsereturn(1);
How
How
How
How
Behavior:
value
reset
state
open/closed
States: 5 states
Represent point in execution of machine
Each state has outputs
Transitions: 6 from state to state, 5 self transitions, 1 global
Changes of state occur when clock says its ok
Based on value of inputs
Inputs: reset, new, results of comparisons
Output: open/closed
ERR
closed
C1!=value
& new
S1
reset
closed
S2
C2!=value
& new
S3
closed
C1=value
& new
not new
C3!=value
& new
closed
C2=value
& new
not new
open
C3=value
& new
not new
OPEN
Data-path
Storage for combination
Comparators
Control
Finite-state machine controller
Control for data-path
State changes controlled by clock
new
value
C1
C2
multiplexer
C3
mux
control
equal
reset
controller
clock
comparator
equal
open/closed
S1
closed
mux=C1 equal
& new
not new
not new
not new
ERR
not equal
not equal not equal
& new
& new
& new
S1
S2
S3
OPEN
closed
closed
closed
open
mux=C1 equal mux=C2 equal mux=C3 equal
& new
& new
& new
not new
reset
1
0
0
0
0
0
0
0
0
0
0
0
new
0
1
1
0
1
1
0
1
1
equal
0
1
0
1
0
1
state
S1
S1
S1
S2
S2
S2
S3
S3
S3
OPEN
ERR
next
state
S1
S1
ERR
S2
S2
ERR
S3
S3
ERR
OPEN
OPEN
ERR
mux
C1
C1
C2
C2
C3
C3
closed
not new
open/closed
closed
closed
closed
closed
closed
closed
closed
closed
closed
open
open
closed
not new
new
0
1
1
0
1
1
0
1
1
equal
0
1
0
1
0
1
state
0001
0001
0001
0010
0010
0010
0100
0100
0100
1000
0000
next
state
0001
0001
0000
0010
0010
0000
0100
0100
0000
1000
1000
0000
mux
001
001
010
010
100
100
open/closed
0
0
0
good choice of encoding!
0
0
mux is identical to
0
last 3 bits of state
0
0
open/closed is
0
identical to first bit
1
of state
1
0
equal
reset
controller
clock
new equal reset
open/closed
mux
control
comb. logic
state
open/closed
clock
Design Hierarchy
digital system
control
data-path
code
registers multiplexer comparator
register
state
registers
combinational
logic
logic
switching
networks
Design Methodology
Structure and Function
(Behavior) of a Design
HDL
Specification
Simulation
Synthesis
Verification: Design
Behave as Required?
Functional: I/O Behavior
Register-Level (Architectural)
Logic-Level (Gates)
Transistor-Level (Electrical)
Timing: Waveform Behavior
Generation: Map
Specification to
Implementation
Registers, Register files (with multiple read and write ports), Shifters,
Counters, RAMs
Arbitrators
Design the control part as one or more interacting Finite State Machines
State Diagrams as well as Verilog for control
Design the datapath blocks
Behavioral Verilog mostly, but gate level hand-drawn schematics for
some selected parts