Silicon on Insulator (SOI)

Based Devices
Amitava DasGupta
Department of Electrical Engineering
I.I.T. Madras
Chennai 600037
adg@ee.iitm.ac.in
1

Why SOI ?
CMOS circuits on SOI
has several
advantages resulting
in lower power and
higher speed
Ideal for radiation
hard devices
Ideal substrate for
high temperature
devices, MEMS
based sensors
SOI devices will allow us to keep
up with Moores Law for a longer
2
period

SOI MOSFET Device of future

SOI MOSFET Structure

S

G1

N+

N+

Buried Oxide
Substrate

G2
4

CMOS - Bulk vs. SOI

Bulk and SOI CMOS structures

Advantages of SOI CMOS

Technology
Simpler technology with no wells or trenches

Device performance
Better dielectric isolation in both vertical and horizontal directions
No latch up
Better radiation tolerance

Advantages of SOI CMOS

Device performance
Reduced capacitance and leakage currents as the
area of the source drain junctions are reduced
Reduced short channel effects allows enhanced
scaling
SOI

Bulk
Field oxide

Drain

Drain
Buried oxide

Field
Implant
Substrate

Substrate
7

Advantages of SOI CMOS

Device performance
Reduced subthreshold swing allows lower voltage
operation

SOI Wafer Types

SOS for Silicon on Sapphire (almost
obsolete)
SIMOX Separation by IMplantation of
Oxygen
Bonded Wafer SOI
BESOI stands Bonded and Etch-back SOI
Smart-Cut process
Eltran process
9

SmartCut process
Hydrogen implantation
through thermal oxide
dose ~1-5e16 cm-2

BOX

B
BOX

BOX
A

H2 peak

At ~400-600C wafer A
separates from B at H2 peak

Handle wafer B
is bonded

A
A

SOI film thickness set by H2 implant energy and BOX thickness

Handle wafer B can be low-grade and cheap
High grade wafer A can be reused many times
Smart Cut SOI wafer can be cheaper than Bulk Silicon Wafer !!!

10

SOI-like structures

11

Common types of SOI MOSFET

12

Energy Band diagrams of Bulk, Partially

Depleted (PD) and Fully Depleted (FD) SOI
MOSFETs
A

Gate oxide

B
Ec

Ec

Ef

Ef

Ev

Ev

C
Ec

Front
gate
oxide

Ef

Ev

Back
gate
oxide

Front
gate
oxide

Back
gate
oxide

Shaded regions are depleted

13

FD MOSFET: Operation Modes

VG1
Front Inversion
Back Accumulation

Front Inversion
Back Depletion
Front Inversion
Back Inversion

Front Depletion
Back Accumulation
Front Depl.
Back Depl.

Front Depletion
Back Inversion
Front Accumulation
Back Accumulation

Front Accum.
Back Depl.

VG2

Front Accumulation
Back Inversion

14

SOI Device structure

Front Gate

tOxf

VGf

Front channel

n+

VD
n+

Back channel

tSi

tOxb

VGb

Back Gate
15

Electric field and Potential

distribution
E
Front surface is always
in inversion
A Back surface is in
accumulation
B Back surface is in
depletion
C Back surface is in
inversion

00

2B

2B

16

Channel Coupling Equations in FD SOI

Solving Poissons equation in the SOI film under fully depleted

condition, we have two equations which describe the coupling
between the two channels

C
C
Q
Vgf VFBf 1 S sf S sb D

Coxf
Coxf
2Coxf

C
C
Q
Vgb VFBb S sf 1 S sb D
Coxb
Coxb
2Coxb

When back channel is in accumulation, sb= 0. Therefore

VgbA VFBb

CS
Q
sf D
Coxb
2Coxb

C
VTHA VFBf 1 S

Coxf

sf QD

2Coxf

17

VTh versus Vgb in FD SOI

When back channel is in inversion, sb= 2B. Therefore

V VFBf
I
Th

C
1 S

Coxf

VgbI VFBb

Hence

sf CS 2 B QD

Coxf
2Coxf

CS
C
Q
sf 1 S 2 B D
Coxb
Coxb
2Coxb

VTh VThA VThI

CS
2B
Coxf

C
Vgb VgbA VgbI 1 S 2 B
Coxb

Slope

CS
Coxf

VTh

Vgb

When toxb>>tSi , Cs>>Coxb ,

CS

Coxb

C S Coxb

Coxf CS Coxb

Coxb toxf

Coxf toxb

18

Effect of Coupling on Threshold

Voltage of FD SOI
A
TH

Front Threshold Voltage

Back Accumulation

Model
Measured
Full depletion
Back Inversion

VTHI

0V

VgbA

VgbI Back Gate Voltage

19

VTh versus Vgb in FD SOI

VTh is independent of toxb
However, VTh becomes less sensitive to Vgb
variation when toxb becomes much larger than toxf
TBOX= 5 nm
TBOX= 10 nm
TBOX= 20 nm
TBOX= 30 nm
TBOX= 40 nm

0.4

VTHF

0.3

-3

Na=4.2e17 cm
TFox=5 nm
TSi=50 nm
VFBF=VFBB=-1 V

0.2

0.1
-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

VGB (V)

20

Transconductance Characteristics of FD SOI

B

Tb

Gf

D
-2

VGb1

Gb2

Gb3

VGb (V)

-4

VGb1

VGb2

VGb3
-6

-30

-20

-10

10

20

More positive
Transconductance, gm

Gb

V VG f T(Vf (V) )

T h re sh o ld v o ltag e (V )

V =V vs V
Gf Tf
Gb
V =V vs V

VG2
Plateau
More negative

Front gate voltage, VG1

30

40

50

Back gate voltage (V)

The plateau in the characteristics indicates the back

channel turning on before the front channel
21

Subthreshold swing (S)

dVGS
S
d log I D
S = change in VGS for unit change in log(ID) OR
S = change in VGS for one decade change in ID
For sharp transition between ON and OFF state,
S should be small
In subthreshold region of operation

I D exp S
VT

log I D K

S
S
K
VT ln(10)
2.3VT

1 d log I D
1 d S

S
dVGS
2.3VT dVGS
S 2.3nVT 60n mV

22

Subthreshold swing (S)

(contd.)
1 d S How well does the gate

n dVGS
control the channel potential?

When control is ideal

When control is bad

d S
1 n 1
dVGS
d S
1 n 1
dVGS

In short channel devices, gate control is

less due to effect of drain n>1
Minimum possible value of S = 2.3VT =

23

Subthreshold swing (S) in PD SOI

VGS
S

Coxf

channel

CD

Bulk, Partially Depleted

Coxf d VGS S CD d S

or , Coxf dVGS Coxf CD d S

dVGS
C
1 D
d S
Coxf

C
S 60 1 D

Coxf

mV

n=1.3 ... 1.5

Note: Interface trapped charges have been neglected

Including Interface trapped charges

CD Citf

S 60 1

Coxf

mV

24

Subthreshold swing (S) in FD SOI

VGS
sf
sb

Coxf

Front channel

Cs
Back channel

COXb

Fully Depleted
n1

Replace CD in the analysis for PD SOI

with series combination of CS and Coxb
dVGS
CS Coxb
n
1
1
d Sf
Coxf CS Coxb

C
C
S
oxb

S 60 1

Coxf CS Coxb

mV

Assuming CSCD

n 1 FD
n 1 PD

Coxb
1

1
C
CS Coxb 1 S
Coxb

So n is much closer to 1 in FD SOI than in PD SOI

A thicker back oxide helps in reducing Subthreshold swing25

Subthreshold slope vs. SOI Thickness

Subthreshold Slope
(mV/dec)

log Drain Current (A)

-4
-6 63 mV/dec
-8

102 mV/dec

-10
-12
-15
-0.5

100nm-thic k film
200nm-thic k film

0.0

0.5

1.0

1.5

Gate Voltage (V)

2.0

120
110
100
90
80

C alculated
Measured

70
60

100
200
300
400
500
Silicon Film Thickness (nm)

600

The subthreshold slope changes drastically in

the transition region from PD to FD SOI
26

Current-Voltage relations
SPICE Level-3 model

I D COX

W
1 2
[(VG VTH )VD VD ]
L
2n

1
W
ID
COX (VG VTH ) 2
2n
L

For FD SOI, n is less than in Bulk or PD SOI

(refer to discuusion on Subthreshold slope)
Current drive is more for FD SOI
27

Electric field (Mobility): FD vs. Bulk

Bulk

Thin FD SOI

-E

-E

xdmax
Depth in silicon (x)

x1

tsi

Depth in silicon (x)

Since transverse electric fields are smaller in

FD devices, mobilities are higher
Also reflected in higher current drive

28

Drive current: FD vs. Bulk and PD SOI

SOI
Bulk

20

IDsat

A )

30

10

2
3
VG1-VTH (V)

5
29

Floating Body Effects (FBEs) in SOI

These effects are due to
- The creation of body charge QB in PD SOI
The source (n+) - body (p) - drain (n+) parasitic
bipolar transistor (PBT) in both PD and FD SOI
-

n+

QB(t)++

n+

e-h pairs generated by impact

ionization. e flow in to the drain, h
accumulate in the floating body near
source QB.
30

DC Current Kink in a PD SOI

Vg=3.4V

ID (mA)

Vg=3.0V
Vg=2.6V

Vg=2.2V
Vg=1.8V

Vg=1.4V

1
0
0

2
VD (V)

3
31

Explanation of DC current Kink

With increase in VD, e-h pairs may be
generated near the drain by impact
ionization.
The electrons flow in to the drain (and
become part of drain current).
In FD SOI, the holes flow to the source
In PD SOI, the holes accumulate in the
floating body due to the higher barrier at
source-substrate junction. This increases
substrate potential, causing the threshold
voltage to decrease

VT VT 0 [ (2 F VSB ) 2 F ]
32

Floating vs. grounded body VTC

3

Vout

V(out)

Grounded
2

Floating
Body:

Vin
0
0

V(in)

The nMOS turns on while Vout is still high

Floating body charges up
Its threshold voltage decreases
The VTC stretches out

33

FBE due to PBT (both PD and FD)

Vds

Front gate

Id
Floating
body

Ich

Drain

Vbs
Substrate (back gate)

Cbox

Iii

Holes generated by impact ionization flow into the neutral body.

This hole current, which is the base current of the parasitic bipolar
transistor (PBT), gets amplified by the PBT beta ().
This leads to:
abnormal subthreshold slope/increased leakage
early breakdown/ single transistor latch
hysterisis in the operation of devices/circuits
34

PBJT induced single transistor latch-up

b

Increased
drain voltage

Log (drain current)

c
b

a
0V

Gate Voltage

(a) Low VD - normal subthreshold slope

(b) Higher VD - Slope increases gradually to infinite. Hysteresis
appears due to reduction in threshold voltage.
(c) Very high VD - Device "latches-up, i.e. does not switch off due
to a large reduction in threshold voltage

35

Single transistor latch-up example

PD SOI

ID (A)

-4
-8

VD=3V
VD=3.3V
VD=3.4V

-12
-16

-2

-1

VG1 (V)

36