Field Effect

Transistors
Intel Pentium 4

Equivalent Circuits

EE314

MOSFET Transistor
1.Small-Signal
Equivalent Circuits
1.Examples
2.Technology
3.Future Devices

Chapter 12: Field

Effect Transistors

0 when vGS Vt 0

2
iD K 2 vGS Vt 0 vDS vDS
when vGS Vt 0 0

K
v

V
when vDS vGS Vt 0 0
GS
t0

Current-Voltage Relations
MOSFET Transistor
6

x 10

-4

VGS= 2.5 V

VDS = VGS - VT

Triode

4
ID (A)

VGS= 2.0 V

VGS= 1.5 V

Quadratic
Relationship

VDS = VGS - VT

cut-off

Saturation

VGS= 1.0 V
0

0.5

VDS (V)

1.5

2.5

NMOS transistor, 0.25m, Ld = 10m, W/L = 1.5, VDD = 2.5V, VT = 0.4V

Load-Line Analysis of NMOS Amplifier

It is a graphical analysis similar to load-line analysis of pn diode.
We look for the
operating point

Schematic

vGS

vDS

Circuit Analysis:
Input
loop

vGS (t ) vin (t ) VGG

vGS (t ) sin( 200t ) 4

Output
loop

VDD RD iD (t ) vDS (t )

Load
line

20 RD iD (t ) vDS (t )

Load-Line Analysis of NMOS Amplifier

Exercise:
Draw the Load line

20 RD iD (t ) vDS (t )

RD= 1 k

vGS 4

vGS 3
vGS 2

Load-Line Analysis of NMOS Amplifier

Load line

vDS vD vS

Taking iD=0 or vDS=0 we find out

the load lane and the quiescent
operating point Q for VGS=4V
The quiescent values

vGS (t ) vin (t ) VGG

vin(t)=0 then iDQ=9 mA
vGSQ=4V and vDSQ=11V
Points A & B
intersection of
curve and the
load-line for the
maximum and the
minimum gate
voltage

Load-Line Analysis of NMOS Amplifier

Input signal vin (t ) 1sin( 200t )

(peak-to-peak amplitude is 2V)

vDS(t)
12V peak-to-peak

2V peak-to-peak

vin(t)

Inverse
operation
The positive peak of the input occurs at the same time as the min. value of
vDS. The output is not a symmetrical sinusoid! (nonlinear distortion)

Self Bias Circuits

Analysis of amplifier circuits is often undertaken in two steps:
(1) The dc circuit analysis to determine the Q point. It involves the
nonlinear equation or the load-line method. This is called bias
analysis

The fixed-plus selfbias circuit

Exercise:

Find VG voltage as a
function of VDD, R1
and R2

vG
_
Input

Output

Self Bias Circuits

Analysis of amplifier circuits is often undertaken in two steps:
(1) The dc circuit analysis to determine the Q point. It involves the
nonlinear equation or the load-line method. This is called bias
analysis

The fixed-plus selfbias circuit

+

VG V DD

R2
R1 R2

vG
_
Input

Output

Self Bias Circuits

Analysis of amplifier circuits is often undertaken in two steps:
(1) The dc circuit analysis to determine the Q point. It involves the
nonlinear equation or the load-line method. This is called bias
analysis
(2) Use a linear small-signal equivalent circuit to determine circuit
parameters

Analysis

VG vGS RS i D

i D K vGS Vt 0

find vGS

Equivalent
circuit

vGS

vDS

Self Bias Circuits

VG vGS RS i D

Plot of

Disregarded root

<

for vGS Vt0

Use only larger

root for vGS and
smaller for iD
Example 12.2

and

i D K vGS Vt 0

Self Bias Circuits

Analysis of amplifier circuits is often undertaken in two steps:
(1) The dc circuit analysis to determine the Q point. It involves the
nonlinear equation or the load-line method. This is called bias
analysis
(2) Use a linear small-signal equivalent circuit to determine circuit
parameters

Analysis

find iD
For saturation region

i D K vGS Vt 0

Equivalent
circuit

v DS V DD RD RS i D

vGS

vDS

Self Bias Circuits

Analyze the self-bias circuit shown.
The transistor has KP=50A/V2,
Vto=2V, L=10m, and W=400m

Exercise 12.5

W KP
K

L 2

VG V DD

R2
R1 R2

VG vGS RS i D

i D K vGS Vt 0

find vGS

find iD

i D K vGS Vt 0

find vDS

v DS V DD RD RS i D

Flexible
Field Effect
Transistors

EE314

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electronics
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Transistor Feature Sizes

http://www.hkn.org/imgs/bridge_sp06_figure2.gif