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Control Unit
Mrs.Rajani.P.K
06/21/15
Control Unit
Single us organization - register transfer,
performing an arithmetic or logic operation,
fetching and storing word from/to memory,
execution of complete instruction , branch
instruction, Multi bus organization, hardware
control design methods state table and
delay element method
A complete processor, Micro-programmed
control microinstructions, micro-program
sequencing, wide branch addressing, microinstructions with next address field, perfecting
microinstructions, emulation
Objectives
To study Single and Multi Bus Organization
Execution of an instruction by generating control
signals
To design control unit
Hardwired Controlled Design
State Table method
Delay Element method
REFERENCE
Book: Computer organization by Hamacher
Chapter 7
Pg 411
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TOPICS TO COVER
Chapter 7: Basic Processing Unit
Single Bus Organization
Register Transfer
Performing an arithmetic or logic operation
Fetching and storing word from/to memory
Multi-bus Organization
Hardwired Control:
Design methods State table and classical method
A complete Processor
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- Continued..
Micro-programmed Control
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Microinstructions
micro- program sequencing
wide branch addressing
microinstructions with next address field
perfecting microinstructions
Emulation.
Recap: Organisation
Bus
Processor
Memory
Control
Cache
Datapath
Registers
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Devices
Input
Output
Fundamental Concepts
Processor (CPU): the active part of the computer,
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Instruction execution
cycle: fetch, decode,
execute.
Fetch: fetch next
Instruction
Fetch
Instruction
Decode
Operand
Fetch
Execute
Result
Store
Next
Instruction
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Processor
Processing unit [Instruction Set ProcessorISP] or Processor:
executes machine instructions and
coordinates the activities of the other units.
It used to be called Central Processing
Unit(CPU).
Central is less appropriate today since
modern computers include several
processing units.
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Address line
Memory
bus
Data line
PC
Control signals
...
MAR
Instruction
decoder
and control
logic
MDR
IR
Y
Constant 4
RO
MUX
Select
ALU
control
lines
Add
Sub
ALU
Carry-in
XOR
TEMP
Z
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:
:
R(n1)
Single-bus Organization
Instructions can be executed by performing one or more of
the following operations:
Register Transfer
Transfer a word of data from one processor register to another or
to the ALU.
Multiple-Bus Organization
Bus A Bus B
Bus C
Bus A Bus B
Bus C
Incrementer
Instruction
decoder
PC
IR
Register
file
MUX
Constant 4
MDR
A
ALU
R
MAR
Address
line
Memory bus
data lines
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Instruction Execution
An instruction can be executed by performing one or more of the
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Register Transfer
(p415)
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Y in
X
Ri
Y
Constant 4
Select
X
Ri out
MUX
A
ALU
Z in
X
Z
X
Z out
All operations & data transfers takes place within time periods called
PROCESSOR CLOCK.
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When Rin=1, MUX selects data on the bus. This data will be loaded into F/F
at rising edge of clk.
When Rin=0, MUX feeds back the value currently stored in F/F.
Q O/P is connected to bus via tri-state gate.
When Riout=0, gates o/p -> high impedence
When Riout=1, gates drives bus to value 0 or 1
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Y in
Ri
Constant
4
X
Ri out
MUX
A
ALU
Z in
X
Z
X
Z out
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Select
Ri in
STEP 1:
Reg R1 o/p and Reg Y I/P are enable
STEP 2:
MUX select signal set to SelectY
So MUX gates the Y contents to I/p A of ALU
At same time-> Contents of R2 are gated onto the bus and hence,
to I/P B of ALU
Here ADD line is set to 1. SO ALU O/P = A+B -> Then o/p into Z
STEP 3:
Contents of Z transferred to Destination Reg R3.
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MDR CONNECTIONS
Memory-bus data
lines
Internal processor
bus
MDR inE
MDR in
X
MDR
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MDR outE
MDR out
/* R2 [[R1]]
1. MAR [R1]
2. Start a Read operation on the memory bus
3. Wait for the control signal MFC(Memory Function completed)
response from the memory
4. Load MDR from the memory bus
5. R2 [MDR]
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Executing a Complete
Instruction
Add (R3), R1
/* R1 [R1] + [[R3]]
Adds the contents of a memory location pointed to by R3
to register R1.
GENERAL STEPS:
1. fetch instruction
2. Fetch 1st operand (contents of memory location pointed by R3)
3. Perform addition
4. Load result into R1
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Steps 1 3:
Instruction
fetch
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FOR CONDITIONAL
4. Offset-field-of-IRout, Add, Zin, If N=0 Then End.
Fetch Cycle ends when instructn loaded into IR
Offset value is extracted from IR by instruction decoding ckt and
gated onto the bus
PC updated value -> in Reg Y -> ALU operand B
Offset -> Bus -> ALU operand A
ADD and O/P into Z -> addr where to branch next
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Multiple-Bus Organization
Single-bus structure: Control sequences are long as only one data
item can be transferred over the bus in a clock cycle.
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Bus C
Bus A Bus B
Bus C
Incrementer
Instruction
decoder
PC
IR
Register
file
MUX
Constant 4
MDR
A
ALU
R
MAR
Address
line
Memory bus
data lines
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STEP 1:
Contents of PC are passed through ALU and stored into MAR to start mem
read operatn. At same time, PC incremented by 4.
Now [MAR] -> original PC value
[PC] -> updated PC value
STEP 2:
Processor waits for MFC and loads data received into MDR.
STEP 3:
STEP 4:
Execution phase of instructn requires only 1 control step.
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Control
Generating of control signals are of 2 categories:
Hardwired control
Microprogrammed control.
Hardwired control:
Clock
CLK
Control step
counter
...
IR
:
:
External
inputs
Condition
codes
Decoder/
encoder
...
Control signals
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Memory bus
data lines
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The ckt that generates the End Control signal from the logic function,
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Hardwired Control
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2.Delay-Element Method
It is heuristic method based on the use of clocked delay element( D FF) for
control signal timings.
4. PLA Method
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State-table method
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State-table method
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State-table method:
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Delay-Element Method
The control signals from the control unit are
activated in a proper seq.
There is specific time delay b/w activation
of 2 groups of consecutive control signals.
A seq. of delay elements can be used to
generate control signals one after the other.
To ensure synchronous operation, the delay
elements are implemented by D FFs
controlled by a common clock signal.
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Delay-Element Method
A control unit using delay elements can be constructed
directly fro the flowchart that specifies required control
signal seq.
Every state requires a delay element.
The signals that activate same control signals are Ored
to get one common o/p signals.
When n lines in the flowchart merge to a common point,
then these lines are an n I/P OR gate.
A decision box can be implemented by 2 I/P AND gate.
The 1st I/P of each AND gate is driven by I/P A and
complement of A respectively.
While 2nd I/P of both gates is common and it is the O/P
of the delay element.
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Delay-Element Method
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Integer
unit
Instruction
cache
Floatingpoint
unit
Data
cache
Businterface
Processor
Systembus
Main
memory
Figure7.14.
Input/
Output
Blockdiagramofacompleteprocessor.
Microprogrammed control
Control signals generated by a program.
Control word (CW) is a microinstruction that contains individual bits
that represent the various control signals.
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Example of a horizontal
5.
6.
7.
4.
R1 in
R3 out
MDRout, IRin
Z out
R1 out
3.
Z in
0
0
1
0
0
0
0
Add
0
0
1
0
0
1
0
1
0
0
1
0
0
0
2.
Select
1
0
0
1
0
0
0
Y in
1
0
0
0
0
0
0
MDR out
IR jn
0
1
0
0
0
0
0
MAR in
Read
PC out
1
2
3
4
5
6
7
..
PC in
Microinstruction
organization scheme:
1.
0
1
0
0
1
0
0
1
0
0
0
0
0
0
1
0
0
0
0
1
0
1
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
0
0
0
0
1
0
1
0
0
1
0
0
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Memory bus
data lines
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
..
Select=0: SelectY
Select=1: Select4
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STEPS
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Figure7.18. Organizationofthecontrolunittoallowconditionalbranchingin
themicroprogram.
External
inputs
IR
Clock
Startingand
branchaddress
generator
Condition
codes
PC
Control
store
CW
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Micro
instruction
PCout
MARin
Read
MDRout
IRin
Yin
Select
Add
Zin
Z out
R1out
R1 in
R3out
WMFC
End
PCin
Figure7.15 AnexampleofmicroinstructionsforFigure7.6.
F2
F3
F4
F5
F1(4bits)
F2(3bits)
F3(3bits)
F4(4bits)
F5(2bits)
0000:Notransfer
0001:PCout
0010:MDRout
0011:Zout
0100:R0out
0101:R1out
0110:R2out
0111:R3out
1010:TEMP
out
1011:Offsetout
000:Notransfer
001:PCin
010:IRin
011:Zin
100:R0in
101:R1in
110:R2in
111:R3in
000:Notransfer
001:MARin
010:MDRin
011:TEMPin
100:Yin
0000:Add
0001:Sub
00:Noaction
01:Read
10:Write
F6
F7
16ALU
functions
F8
F6(1bit)
F7(1bit)
F8(1bit)
0:SelectY
1:Select4
0:Noaction
1:WMFC
0:Continue
1:End
Figure7.19.
1111:XOR
Anexampleofapartialformatforfieldencodedmicroinstructions.
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Further Improvement
Enumerate the patterns of required signals in all possible
microinstructions.
Each meaningful combination of active control signals
can then be assigned a distinct code that represents the
microinstruction.
Such full encoding further reduces microword lengths but
increases complexity of decoder ckts.
Vertical organization
Horizontal organization
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Microprogram Sequencing
If all microprograms require only straightforward
sequential execution of microinstructions except for
branches, letting a PC governs the sequencing
would be efficient.
However, two disadvantages:
Having a separate micro-routine for each machine instruction results
in a large total number of microinstructions and a large control store.
Longer execution time because it takes more time to carry out the
required branches.
Eg: Add src, Rdst (Adds source operand with Rdst reg contents)
Assume source operands can be specified in Four addressing
modes: register, autoincrement, autodecrement, and indexed (with
indirect forms of all 4).
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Mode
ContentsofIR
OPcode
11 10
Rsrc
8 7
Rdst
4 3
Address
(octal)
Microinstruction
000
001
Zout,PCin,Yin,WMFC
002
MDRout,IRin
003
Branch{ PC 101(fromInstructiondecoder);
Note:
121
Rsrcout,MARin ,Read,Select4,Add,Z
in
122
Zout,Rsrcin
123
170
MDRout,MARin,Read,WMFC
171
MDRout,Yin
172
Rdstout ,SelectY,Add,Zin
173
Zout,Rdstin,End
Figure7.21. MicroinstructionforAdd(Rsrc)+Rdst.
Microinstructionatlocation170isnotexecutedforthisaddressingmode.
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External
Inputs
Condition
codes
Decodingcircuits
AR
Controlstore
I R
Nextaddress
Microinstructiondecoder
Controlsignals
Figure7.22.Microinstructionsequencingorganization.
Microinstruction
F0
F1
F0(8bits)
F1(3bits)
Addressofnext
000:Notransfer
microinstruction 001:PCo ut
010:MDRo ut
011:Zo ut
100:Rsrcout
101:Rdstout
110:TEMPou t
F4
F5
F2
F3
F2(3bits)
F3(3bits)
000:Notransfer
001:PCin
010:IRin
011:Zin
100:Rsrcin
101:Rdstin
000:Notransfer
001:MARin
010:MDRin
011:TEMPin
100:Yin
F6
F7
F4(4bits)
F5(2bits)
F6(1bit)
F7(1bit)
0000:Add
0001:Sub
00:Noaction
01:Read
10:Write
0:SelectY
1:Select4
0:Noaction
1:WMFC
F9
F10
1111:XOR
F8
F8(1bit)
F9(1bit)
F10(1bit)
0:NextAdrs
1:InstDec
0:Noaction
1:ORmo de
0:Noaction
1:ORind src
Figure7.23.
FormatformicroinstructionsintheexampleofSection7.5.3.
Implementation of the
Microroutine
Octal
address
0
0
0
0
0
0
0
0
0
0
0
0
1 2 1
1 2 2
0 1 0 1 0 0 1 0 1 0 0 01 1 0 0 1 0 0 0 0 01
0 1 1 1 1 0 0 0 0 1 1 10 0 0 0 0 0 0 0 0 00
1
0
0
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
0
0
1
1
0
1
1
0
1
1
1
0
0
0
0
1
1
01
00
01
00
00
00
01
10
1
1
0
0
0
0
1
1
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F6 F7 F8 F9 F10
0
0
0
0
1
1
1
0
0
0
0
0
F5
0
0
0
1
1
1
1
0
0
0
0
0
F4
0
0
0
1
1
1
1
0
0
0
0
0
F3
0
1
0
0
1
1
1
0
0
0
0
0
F2
1
0
0
0
0
1
2
3
0
0
0
0
F1
1
0
0
0
7
7
7
7
0
1
2
3
F0
0
0
0
0
1
0
0
0
Figure7.24.ImplementationofthemicroroutineofFigure7.21usinga
nextmicroinstructionaddressfield. (SeeFigure7.23forencodedsignals.)
Prefetching
Drawback of microprogrammed control:
Leads to slower operating speed becoz of the time it takes
to fetch microinstructions from control store.
Faster operation is achieved if next instruction is prefetched
while current one is being operated.
Thus execution time can be overlapped with fetch time.
Some difficulties:
Status flags and result of currently executed microinstructns
are needed to determine addr of next microinstructn.
Thus straightforward prefetching occasionally prefetches a
wrong microinstructn.In such cases, fetch must be repeated
with correct addr.
EMULATION
If we add to the instructn set of Computer M1, an entire new
set of instructions which belong to computer M2,Programs
written in m/c language of M2 can then be run on computer
M1 i.e M1 emulates M2.
Emulation allows to replace obsolete equipment with more upto-date machines.
If replacement computer fully emulates original one, then no
s/w changes is to be made to run existing programs.
Thus emulation facilitates transitions to new computer
systems with minimal disruption.
Emulation easy with computers having same architectures but
can succeed with those having totally different architectures.
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EMULATION
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COMPARE SIMULATOR&
EMULATOR
A simulator is a software that duplicates some processor
in almost all the possible ways.
An emulator is a hardware which duplicates the features
and functions of a real system, so that it can behave like
the actual system. Difference between model and real
system operation called-> credibility gap