Memory devices

General types of memory

RAM
ROM
Common memory pin connections
Address connections
Data connections
Selection connections
Control connections

ADDRESS CONNECTIONS

Selects memory locations within the memory device

Labelled from A0 to An
10

address pins A0 to A9

No

of address pins found on memory device is

determined by no of memory locations found
within it.
1K memory device 10 address pins(A0-A9)-uses
10 address i/ps to select any of its 1024 memory
locations.
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DATA CONNECTIONS

Points at which
Data

entered for storage

Extracted for reading

Contains set of data outputs or input/outputs

Bidirectional common i/p or output pin
Labelled as D0 through D7
Representation-1Kx8 bit memory device-8K memory device

SELECTION CONNECTIONS
Enables/selects memory device
Also called

chip

select(CS)
Chip enable (CE)/select(S)
If these pins active-perform read /write operation
Inactive-donot perform
RAM

memory atleast one CS or S i/p

ROM memoryatleast one CE

ROM only one control input

RAM has one/two control input
CASE 1:on ROM output enable(OE) or gate(G) connection
allows data flow out of the output data pin
OE active- output is enabled
OE inactive-output disabled
CASE 2: on RAM
If only one control i/p ------------R/W
If 2 control inputs----------WE or w
OE or G
WE active-perform a memory write
OE active-perform read operation

Other common types of memory

ROM
EEPROM-Flash memory
SRAM
DRAM

Permanently stores program & data

Non volatile
Types of ROMS
EPROM: Erasable Programmable Read only Memory

Used

when s/w must be changed often

When too few are in demand to make the ROM economical
PROM:

Programmable Read only Memory

Programmed by burning open tiny NI-chrome or silicon

oxide fuses, but once it is programmed cannot be erased.
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RMM: Read Mostly Memory/Flash memory/

EEPROM(Electrically erasable programmable ROM)/
EAROM(Electrically alterable ROM)/
NOVROM(Non Volatile ROM)
Electrically erasable in the system, but require more time to
erase than normal RAM
Used to store set up information for systems
Contains password stored in it
Memory cards for digital cameras memory in Mp3 audio
players.

SRAM(Static RAM devices)

Retain data for long as DC power is applied

Static memory: No special actions are required to retain stored
data

Volatile memory will not retain data without power

Stores temporary data-used when size of the Read/Write

memory is relatively small.
Largest static RAM available is 1M x 8

Difference b/w RAM & ROM

RAM

written under normal operations

ROM is programmed outside the computer & is only to read.

DRAM(Dynamic RAM Memory)

Available

in larger sizes upto 256M x 8

Same as SRAM, except it retains data for only 2 or 4ms on
an integrated capacitor.
After 2 or 4 ms contents must be re-written, since capacitor
lose charges
Refreshing of entire memory happens with 256 reads in a 2
or 4ms interval
DISADVANTAGE: Requires so many address pins.

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12

3 methods to transfer data from one device to other exists

in micro computers.

Programmed I/O or Basic I/O

Hand shaking I/O

When data transferred between two devices is based

on the execution of data transfer program
without exchanging any handshake signals before or
after data transfer.
Before transferring the data between two devices , few
hand shaking signals are exchanged.
To ensure the readiness of device for the upcoming
data
Few hand shaking signals are exchanged after the data
transfer to signal the receiving side that data transfer is
finished

Direct memory access (DMA)

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Very popular low cost interfacing component

8255 has 24 input/output pins in all, divided into three 8-bit
ports
Port A and port B can be used as 8-bit input/output ports
Port C can be used as an 8-bit input/output port or as two 4-bit
input/output ports or to produce handshake signals for ports A
and B.

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Eight data lines (D0 - D7)

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82C55 : Pin Layout

Eight data lines (D0 - D7) are available (with an 8-bit data
buffer) to read/write data into the ports or control register
RD (pin 5) and WR (pin 36), which are active low
signals for read and write operations respectively
The control signal CS (pin 6) is used to enable the 8255
chip
active low signal, i.e., when CS = '0', the 8255
is enabled
The RESET input (pin 35) is connected to the
RESET line of system like 8085, 8086, etc., so
that when the system is reset, all the ports are
initialized as input lines

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Group A and Group B control:

Group A and B get the Control Signal from CPU and send the
command to the individual control blocks.

Group A send the control signal to port A and Port C

(Upper) PC7-PC4.

Group B send the control signal to port B and Port C

(Lower) PC3-PC0.

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There are two basic operational modes of 8255:

Input/output Mode (I/O Mode).
Bit set/reset Mode (BSR Mode).

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Input/output mode is selected when D7 bit of the Control Word Register is 1

There are three I/O modes:
Mode 0 - Simple I/O
Mode 1 - Strobed I/O
Mode 2 - Strobed Bi-directional I/O
D0, D1, D3, D4 are assigned for lower port C, port B, upper port C and port
A respectively. When these bits are 1, the corresponding port acts as an
input port.
if D0 = D4 = 1, then lower port C and port A act as input ports
If D0 = D4 = 0 then the corresponding port acts as an output
port
if D1 = D3 = 0, then port B and upper port C act as output ports.
D2 is used for mode selection of Group B
When D2 = 0, mode 0 is selected
When D = 1, mode 1 is selected.

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D5 & D6 are used for mode selection of Group A

The selection is done as follows:

For example, if port B and upper port C have to be initialized as

input ports and lower port C and port A as output ports (all in mode
0):
Since it is an I/O mode, D = 1.
7
Mode selection bits, D2, D5, D6 are all 0 for mode 0
operation.
Port B and upper port C should operate as Input ports,
hence, D1 = D3 = 1.
Port A and lower port C should operate as Output ports,
hence, D4 = D0 = 0.

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FOR BIT SET/RESET MODE : This is bit set/reset

control word format . Command Byte B(Port C only)
D7

D6

D5

D4

D3

D2

D1

D0

BIT SET/RESET
1=SET
0=RESET

X X X
Dont care

Bit select

B1
B2

1 2 34

5 6 7

1 0 10

1 0 1

0 1 10

0 1 1

0 0 01

1 1 1

B0

BIT SET/RESET
FLAG
=0 Active

FOR BIT SET/RESET MODE:

The Bit Set/Reset (BSR) mode is applicable to port C only

Each line of port C (PC0 - PC7) can be set/reset by suitably loading the control
word register
BSR mode and I/O mode are independent and selection of BSR mode does not
affect the operation of other ports in I/O mode.
D7 bit is always 0 for BSR mode.
Bits D6, D5 and D4 are don't care bits.
Bits D3, D2 and D1 are used to select the pin of Port C.
Bit D0 is used to set/reset the selected pin of Port C

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FOR BIT SET/RESET MODE:

As an example,
if it is needed that PC5 be set, then in the control word,
Since it is BSR mode, D7 = '0'.
Since D4, D5, D6 are not used, assume them to be '0'.
PC5 has to be selected, hence, D3 = '1', D2 = '0', D1 = '1'.
PC5 has to be set, hence, D0 = '1'.

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Mode 0
the ports can be used for simple I/O operations
without handshaking signals
Port A, port B provide simple I/O operation
the two halves of port C are independent

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Micro processor & assembly language

Port A

Upper C

Lower C

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Port B

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Micro processor & assembly language

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This mode provides simple input and

output operations for each of the
three ports.
No handshaking is required, data is
simply written to or read from a
specified port.

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Port A provides the segment data

inputs to display and port B provides
a means of selecting one display
position at a time.
Different values are displayed in
each digit via fast time division
multiplexing.

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Micro processor & assembly language

Data saved
as

Row #

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Col #
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When a key is depressed, its contact

bounces for a short period of time. This
problem is overcome by either using
hardware de-bouncer or sampling the
key second time a bit later to assure
that the same key is depressed.

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Techniques to overcome the problem

1. Two key lock out:
During the second scan (after bouncing time is over),
if still two keys of a row are found depressed, both
keys will be locked out & neither is accepted by the
P. However if any one of them is released after
first scan, the second key still depressed will be
accepted by P.
2. N key roll over:
During the second scan (after bouncing time is over),
if still more than one key is found depressed, they
are accepted by the P. The key entries are
accepted in the order in which they were pressed.

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This functional configuration

provides a means for transferring
I/O data to or from a specified port
in conjunction with strobes or
handshaking signals.
In mode 1, Port A and Port B use
the lines on Port C to generate or
accept these handshaking signals

Micro processor & assembly language

Group A
Port A

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Group B
Upper C

Lower C

Port B

Hand shaking
signals
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Two Groups (Group A and Group B).

The 8-bit data port can be either input or
output.
Pins of port C provide Hand shaking
signals.

36

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Keyboard encoder encodes the key-switch into

8 bit ASCII code whenever a key is depressed.
DAV (Data Available) is activated on a key
press, strobing the ASCII-coded key code into
Port A.

8086
INTR

PC 3

PC 5

IBF (input buffer

full)
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~STB : The strobe input loads data into the port

latch on a 0-to-1 transition.
IBF : Input buffer full is an output indicating that the
input latch contain information.
INTR : Interrupt request is an output that requests
an interrupts.
INTE : The interrupt enable signal is neither an input
nor an output; it is an internal bit programmed via
the PC4 (port A) or PC2 (port B) bits.
PC7,PC6 : The port C pins 7 and 6 are general
purpose I/O pings that are available for any purpose.

Signal definitions for Mode 1 Strobe Input

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Printer

8255
PB0

8086

PB7
INTR

PC 0

ACK
PC2

ACK

PC41

DS

Data Strobe : to tell

the printer to latch the
incoming data.
Generated Externally

11-40
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~OBF : Output buffer full is an output that goes low

when data is latched in either port A or port B. Goes
low on ~ACK.
~ACK : The acknowledge signal causes the ~OBF
pin return to 0. This is a response from an external
device.
INTR : Interrupt request is an output that requests
an interrupt.
INTE : The interrupt enable signal is neither an input
nor an output; it is an internal bit programmed via
the PC6(Port A) or PC2(port B) bits.
PC5,PC4 : The port C pins 5 and 4 are generalpurpose I/O pins that are available for any purpose.

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Uni directional port with

or without handshaking

Port A

Bidirectional 8 bit
I/O port

C7-C3

Port B

Hand shaking
signals

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In this mode data is transmitted in both

directions between the 8255 & the
peripheral devices on port A.
Handshaking signals are provided to
maintain proper bus flow discipline in a
similar manner to MODE 1.
Port B can be only configured for mode 0
or 1.

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Timing

diagram is a combination of the Mode 1 Strobed Input and Mode

1 Strobed Output Timing diagrams.